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Each Zeppelin provides 32 Gen 3.0 [[PCIe]] lanes for a total of 128 lanes. In a single-socket configuration, all 128 lanes may be used for general purpose I/O - for example 6 GPUs over x16 and x8 more lanes for additional storage. This is considerably more than any comparable contemporary [[Intel]] model (either {{intel|Broadwell EP|l=core}} or {{intel|Skylake SP|l=core}}). {{amd|Naples|l=core}}-based processors scale all the way up to [[32 cores]] with 64 [[threads]] (for up to 64 cores and 128 threads per complete system). The caveat is that when in 2-way MP mode, half of the lanes are lost. 64 of the 128 of the PCIe lanes get allocated for interchip communication via AMD's {{amd|Infinity Fabrics}} protocols with the remaining 64 lanes left for the system. 64 PCIe lanes for socket-to-socket communication provides a maximum bandiwdth of This setup still leaves the system with 128 PCIe lanes, but it's not any more than in a single-socket configuration. | Each Zeppelin provides 32 Gen 3.0 [[PCIe]] lanes for a total of 128 lanes. In a single-socket configuration, all 128 lanes may be used for general purpose I/O - for example 6 GPUs over x16 and x8 more lanes for additional storage. This is considerably more than any comparable contemporary [[Intel]] model (either {{intel|Broadwell EP|l=core}} or {{intel|Skylake SP|l=core}}). {{amd|Naples|l=core}}-based processors scale all the way up to [[32 cores]] with 64 [[threads]] (for up to 64 cores and 128 threads per complete system). The caveat is that when in 2-way MP mode, half of the lanes are lost. 64 of the 128 of the PCIe lanes get allocated for interchip communication via AMD's {{amd|Infinity Fabrics}} protocols with the remaining 64 lanes left for the system. 64 PCIe lanes for socket-to-socket communication provides a maximum bandiwdth of This setup still leaves the system with 128 PCIe lanes, but it's not any more than in a single-socket configuration. | ||
− | In addition to PCIe lanes, each Zeppelin provides a memory controller supporting dual-channel [[ECC]] DDR4 memory. With EPYC packing 4 | + | In addition to PCIe lanes, each Zeppelin provides a memory controller supporting dual-channel [[ECC]] DDR4 memory. With EPYC packing 4 suck dies, each chip sports 4 memory controllers supporting up 16 DIMMs of 2 [[TiB]] octa-channel DDR4 ECC memory. |
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Facts about "Zen - Microarchitectures - AMD"
codename | Zen + |
core count | 4 +, 6 +, 8 +, 16 +, 24 +, 32 + and 12 + |
designer | AMD + |
first launched | March 2, 2017 + |
full page name | amd/microarchitectures/zen + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | Zen + |
pipeline stages | 19 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |