Editing amd/microarchitectures/zen+

{{amd title|Zen+|arch}}
{{microarchitecture
|atype=CPU
|name=Zen+
|designer=AMD
|manufacturer=GlobalFoundries
|introduction=April 2018
|process=12 nm
|cores=2
|cores 2=4
|cores 3=6
|cores 4=8
|cores 5=12
|cores 6=16
|type=Superscalar
|oooe=Yes
|speculative=Yes
|renaming=Yes
|stages=19
|decode=4-way
|isa=x86-64
|extension=MOVBE
|extension 2=MMX
|extension 3=SSE
|extension 4=SSE2
|extension 5=SSE3
|extension 6=SSSE3
|extension 7=SSE4.1
|extension 8=SSE4.2
|extension 9=POPCNT
|extension 10=AVX
|extension 11=AVX2
|extension 12=AES
|extension 13=PCLMUL
|extension 14=RDRND
|extension 15=F16C
|extension 16=BMI
|extension 17=BMI2
|extension 18=RDSEED
|extension 19=ADCX
|extension 20=PREFETCHW
|extension 21=CLFLUSHOPT
|extension 22=XSAVE
|extension 23=SHA
|extension 24=CLZERO
|l1i=64 KiB
|l1i per=core
|l1i desc=4-way set associative
|l1d=32 KiB
|l1d per=core
|l1d desc=8-way set associative
|l2=512 KiB
|l2 per=core
|l2 desc=8-way set associative
|l3=2 MiB
|l3 per=core
|l3 desc=16-way set associative
|predecessor=Zen
|predecessor link=amd/microarchitectures/zen
|successor=Zen 2
|successor link=amd/microarchitectures/zen 2
|succession=Yes
}}
'''Zen+''' (Zen Plus) is a planned [[microarchitecture]] being developed by [[AMD]] as a successor to {{\\|Zen}}. Zen+ is expected to be succeeded by {{\\|Zen 2}}.

Zen+ based processors are sold under the brand {{amd|Ryzen}} 2nd Generation.

== History ==
[[File:amd zen+ roadmap.png|right|500px]]
Zen+ is set to succeed {{\\|Zen}} in April of 2018. Zen+ will feature the same core as Zen but will take advantage of the new [[GlobalFoundries]]' 12nm process to deliver higher clock speeds and improved power consumption. Zen+ was initially mentioned by AMD's senior fellow and lead architect of Zen, Michael Clark, during Hot Chips 28 in [[2016]] as part of AMD's continuing commitment in the high-performance computing market.

== Codenames ==
{{future information}}

{| class="wikitable"
|-
! Core !! C/T !! Target
|-
| {{amd|Pinnacle Ridge|l=core}} || Up to 8/16 || Mainstream to high-end desktops & enthusiasts market processors
|}

== Process Technology ==
{{see also|12 nm process}}
Zen is manufactured on [[Global Foundries]]' [[12 nm process]] Leading-Performance (12LP), an enhanced version of their 14nm process. The enhanced process is set to provide as much as 15% higher density and 10% higher performance. 12LP brings around a 10% frequency bump for the {{amd|Ryzen}} lineup at the same power envelopes.

== Compatibility ==
[[Linux]] added initial support for Zen starting with Linux Kernel 4.10. [[Microsoft]] will only support Windows 10 for Zen.

{| class="wikitable"
! Vendor !! OS  !! Version !! Notes
|-
| rowspan="3" | [[Microsoft]] || rowspan="3" | Windows || style="background-color: #ffdad6;" | Windows 7 || No Support
|-
| style="background-color: #ffdad6;" | Windows 8 || No Support
|-
| style="background-color: #d6ffd8;" | Windows 10 || Support
|- 
| Linux || Linux || style="background-color: #d6ffd8;" | Kernel 4.10 || Initial Support
|}

== Compiler support ==
Zen+ is largely the same architecture as {{\\|Zen}} and thus uses the same compiler switches.
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable
|-
| [[AOCC]] || <code>‐march=znver1</code> || <code>-mtune=znver1</code>
|-
| [[GCC]] || <code>-march=znver1</code> || <code>-mtune=znver1</code>
|-
| [[LLVM]] || <code>-march=znver1</code> || <code>-mtune=znver1</code>
|-
| [[Visual Studio]] || <code>/arch:AVX2</code> || ?
|}

=== CPUID ===
{| class="wikitable tc1 tc2 tc3 tc4"
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
|-
| rowspan="2" | {{amd|Pinnacle Ridge|l=core}} || 0x8 || 0xF || 0x0 || 0x8
|-
| colspan="4" | Family 23 Model 8
|-
| rowspan="2" | {{amd|Picasso|l=core}} ||  0x8  || 0xF ||  0x0  || 0x18
|-
| colspan="4" | Family 23 Model 24
|}

== Release Dates ==
AMD intends on launching 2nd generation {{amd|Ryzen}} in April of 2018. 2nd Generation {{amd|Ryzen Threadripper}} and Ryzen PRO processors will launch in the second half of 2018.


[[File:amd ryzen 2018 roll-out.png|1000px]]

== Architecture ==
[[File:amd zen+ perf improvement.png|right|500px]]
Serving as a light refresh over {{\\|Zen}}, those processors have around ten percent higher base frequency for the same power envelope.

=== Key changes from {{\\|Zen}} ===
* ~10% higher [[clock]] frequency
* [[12 nm process]] (from [[14 nm]])
* {{amd|Precision Boost 2}} (from Precision Boost)
* {{amd|XFR 2}} (from XFR 1)
* Cache
** Improved cache prefetch
** 12 cycle L2 latency for mainstream desktop (from 17 cycles)
* Memory
** Higher DDR4 transfer rate (2933 MT/s from 2666 MT/s)
* Mainstream chipsets (See [[#Sockets/Platform|§ Sockets/Platform]])
** X370 → X470
*** Lower Power
*** Bug fixes
*** OEM related issues resolved (unspecified)

=== Block Diagram ===
===== Entire SoC Overview =====
[[File:zen soc block.svg|600px]]
===== Individual Core =====
[[File:zen block diagram.svg|900px]]

=== Memory Hierarchy ===
* Cache
** L0 µOP cache:
*** 2,048 µOPs, 8-way set associative
**** 32-sets, 8-µOP line size
*** Parity protected
** L1I Cache:
*** 64 KiB 4-way set associative
**** 256-sets, 64 B line size
**** Shared by the two threads, per core
*** Parity protected
** L1D Cache:
*** 32 KiB 8-way set associative
**** 64-sets, 64 B line size
**** Write-back policy
*** 4-5 cycles latency for Int
*** 7-8 cycles latency for FP
*** SEC-DED ECC
** L2 Cache:
*** 512 KiB 8-way set associative
*** 1,024-sets, 64 B line size
*** Write-back policy
*** Inclusive of L1
*** 12 cycles latency
*** DEC-TED ECC
** L3 Cache:
*** Victim cache
*** Summit Ridge, Naples: 8 MiB/CCX, shared across all cores.
*** Raven Ridge: 4 MiB/CCX, shared across all cores.
*** 16-way set associative
**** 8,192-sets, 64 B line size
*** 40 cycles latency
*** DEC-TED ECC
** System DRAM:
*** 2 channels per die
*** Summit Ridge: up to PC4-21300U (DDR4-2666 UDIMM)
*** Raven Ridge: up to PC4-23466U (DDR4-2933 UDIMM)
*** Naples: up to PC4-21300L (DDR4-2666 RDIMM/LRDIMM)
*** ECC support: x4 DRAM device failure correction (Chipkill), x8 SEC-DED ECC, Patrol and Demand scrubbing, Data poisoning

Zen TLB consists of dedicated level one TLB for instruction cache and another one for data cache.

* TLBs
** ITLB
*** 8 entry L0 TLB, all page sizes
*** 64 entry L1 TLB, all page sizes
*** 512 entry L2 TLB, no 1G pages
*** Parity protected
** DTLB
*** 64 entry L1 TLB, all page sizes
*** 1,532-entry L2 TLB, no 1G pages
*** Parity protected

== Core ==
=== Pipeline ===
Zen+ pipeline is identical to {{\\|Zen#Pipeline|Zen's}}.

=== Memory Subsystem ===
When AMD presented their paper at ISSCC 2018, WikiChip was able to confirm with AMD's SoC architect that {{\\|Zen|Zen's}} L2 latency was always designed to be 12 cycles. In fact all Zen-based microprocessors (including {{amd|EPYC}}, {{amd|Ryzen Threadripper}}, and Zen-based APUs) have an L2 latency of 12 cycles for all patterns. Only mainstream Zen-based {{amd|Ryzen}} processors (i.e., {{amd|Summit Ridge|l=core}}) have a latency of 17 cycles. The problem has been sorted out with Zen+.

== Sockets/Platform ==
All Zen+-based mainstream consumer microprocessors utilizes AMD's {{amd|Socket AM4}}, a unified socket infrastructure. All those processors are a complete [[system on a chip]] integrating the [[northbridge]] ([[memory controller]]) and the [[southbridge]] including 16 [[PCIe]] lanes for the [[GPU]], 4 PCIe lanes for the [[NVMe]]/SATA controllers as well as USB 3.0. The chipset, however, extends the processor with a number of additional connections beyond that offered by the SoC. 

{{amd socket am4 chipsets}}

== All Zen+ Chips ==
{{future info}}
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc6 tc7">
{{comp table header|main|11:List of all Zen+ based Processors}}
{{comp table header|cols|Price|Launched|Family|Core|%Cores|%Threads|L2$|L3$|%Frequency|%Boost|%TDP}}
{{#ask: [[Category:microprocessor models by amd]] [[microarchitecture::Zen+]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?microprocessor family
 |?core name
 |?core count
 |?thread count
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |format=template
 |template=proc table 3
 |userparam=13
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[microarchitecture::Zen+]]}}
</table>
{{comp table end}}

== References ==
* AMD CES Tech Day 2018, Jim Anderson
* AMD CES Tech Day 2018, Lisa Su
* AMD CES Tech Day 2018, Mark Papermaster

== Documents ==
* [[:File:AMD CES Tech Day 2018 Jim Anderson.pdf|AMD Tech Day 2018, Jim Anderson]]
* [[:File:AMD CES Tech Day 2018 Lisa Su.pdf|AMD Tech Day 2018, Lisa Su]]
* [[:File:AMD CES Tech Day 2018 Mark Papermaster.pdf|AMD Tech Day 2018, Mark Papermaster]]

== See Also ==
* Intel {{intel|Coffee Lake|l=arch}}
codename	Zen+ +
core count	4 +, 6 +, 8 +, 12 +, 16 +, 24 +, 32 + and 1 +
designer	AMD +
first launched	April 13, 2018 +
full page name	amd/microarchitectures/zen+ +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	GlobalFoundries +
microarchitecture type	CPU +
name	Zen+ +
pipeline stages	19 +
process	12 nm (0.012 μm, 1.2e-5 mm) +