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{{amd title|K7|arch}}
 
{{amd title|K7|arch}}
 
{{microarchitecture
 
{{microarchitecture
|atype=CPU
+
| name             = K7
|name=K7
+
| designer         = AMD
|designer=AMD
+
| manufacturer     = AMD
|manufacturer=AMD
+
| introduction     = June 23, 1999
|introduction=June 23, 1999
+
| phase-out        =
|process=250 nm
+
| process         = 250 nm
|process 2=180 nm
+
| process 2       = 180 nm
|process 3=130 nm
+
 
|cores=1
+
| succession      = Yes
|type=Superscalar
+
| predecessor     = K6-III
|oooe=Yes
+
| predecessor link = amd/microarchitectures/k6-iii
|speculative=No
+
| successor       = K8
|renaming=Yes
+
| successor link   = amd/microarchitectures/k8
|stages min=10
 
|stages max=15
 
|isa=x86-32
 
|extension=MMX
 
|extension 2=Extended MMX
 
|extension 3=3DNow!
 
|extension 4=Extended 3DNow!
 
|extension 5=SSE
 
|l1i=64 KiB
 
|l1i desc=2-way set associative
 
|l1d=64 KiB
 
|l1d desc=2-way set associative
 
|l2=256 or 512 KiB
 
|l2 desc=16-way set associative
 
|core name=Spitfire
 
|core name 2=Morgan
 
|core name 3=Camaro
 
|core name 4=Appaloosa‎‎
 
|core name 5=Applebred
 
|core name 6=Palomino
 
|core name 7=Thoroughbred
 
|core name 8=Barton
 
|predecessor=K6-III
 
|predecessor link=amd/microarchitectures/k6-iii
 
|successor=K8
 
|successor link=amd/microarchitectures/k8
 
|pipeline=Yes
 
|OoOE=Yes
 
|issues=3
 
|inst=Yes
 
|cache=Yes
 
|core names=Yes
 
|succession=Yes
 
 
}}
 
}}
'''K7''' was the [[microarchitecture]] for [[AMD]]'s {{amd|Athlon}} and {{amd|Duron}} families of microprocessors as a successor to the {{\\|K6-III}}. K7 was superseded by {{\\|K8}} in 2003.
+
'''K7''' was the [[microarchitecture]] for [[AMD]]'s {{amd|K6-III}} line of microprocessors as a successor to the {{\\|K6-III}}. K7 was superseded by {{\\|K8}} in 2003. K7 was used for AMD's {{amd|Athlon}} and {{amd|Duron}} families of processors.
  
 
== Codenames ==
 
== Codenames ==
Line 59: Line 26:
 
| {{amd|Morgan|l=core}} || {{amd|Duron}} || 2nd generation Duron, introduced SSE & Hardware data prefetcher
 
| {{amd|Morgan|l=core}} || {{amd|Duron}} || 2nd generation Duron, introduced SSE & Hardware data prefetcher
 
|-
 
|-
| {{amd|Camaro|l=core}} || {{amd|Duron}} || Former corename for 2nd generation (Morgan) mobile processors
+
| {{amd|Applebred|l=core}} || {{amd|Duron}} ||
|- style="text-decoration: line-through"
 
| {{amd|Appaloosa‎‎|l=core}} || {{amd|Duron}} || Scheduled to be 3rd generation, scrapped for unknown reasons
 
|-
 
| {{amd|Applebred|l=core}} || {{amd|Duron}} || 3rd generation Duron, produced on a newer [[130 nm process]]
 
|-
 
| {{amd|Palomino|l=core}} || {{amd|Athlon MP}}<br>{{amd|Athlon XP}} || 1st generation Athlon XP/MP performance processors
 
 
|-
 
|-
| {{amd|Thoroughbred|l=core}} || {{amd|Athlon MP}}<br>{{amd|Athlon XP}} || 2nd generation Athlon XP/MP performance processors
+
| {{amd|Camaro|l=core}} || {{amd|Duron}} ||  
|-
 
| {{amd|Barton|l=core}} || {{amd|Athlon MP}}<br>{{amd|Athlon XP}} || 3rd generation Athlon XP/MP performance processors
 
 
|}
 
|}
 
== Process Technology ==
 
K7 was originally manufactured on AMD's [[180 nm process]]. By late 2002, AMD transitioned to a [[130 nm process]].
 
  
 
== Architecture ==
 
== Architecture ==
K7 was a relatively new design by [[AMD]] which marked a departure from the aging [[Socket 7]] and [[Super Socket 7]]. The new architecture introduced a number of major changes including a new propietary unified [[Socket A]].
+
{{empty section}}
 
 
=== Key changes from {{amd|K6|l=arch}} / {{amd|K6-III|l=arch}} ===
 
* System Bus
 
** K7 utilizes the [[Digital Alpha]] {{decc|EV6}} system bus interface
 
*** AMD licensed the technology from Digital allowing them to independently develop their own [[chipsets]] and [[motherboards]] without paying licensing fees to [[Intel]] for their [[Slot 1]] {{intel|GTL+}} bus. This does consequently meant incompatibility AMD's motherboards and Intel's motherboards.
 
*** The EV6 utilizes [[double data rate]] (DDR) doubling the effective data transfer rate of the bus speed.
 
*** 100 MHz bus = 200 [[MT/s]]
 
*** 133 MHz bus = 266 [[MT/s]]
 
 
 
=== Memory Hierarchy ===
 
AMD used a split L1$ and a unified L2$. While originally K7 had an L2$ controller on-die with the actual cache off-chip, AMD moved the L2$ on-die the following year.
 
* Cache
 
** L1 Cache:
 
*** 64 [[KiB]] 2-way set associative instruction, 64 B line size
 
*** 64 KiB 2-way set associative instruction, 64 B line size
 
** L2 Cache:
 
*** 64 KiB 16-way set associative, 64 B line size
 
*** Unified
 
*** 7 cycles latency
 
*** 64-bit data bus
 
*** exclusive
 
*** '''Note''' original {{amd|Athlon}} models did not feature an on-die L2$, instead cache was implemented off-chip with a built-in controller supporting up to 8 [[MiB]] OF [[single data rate|SDR]]/[[double data rate|DDR]] [[SRAM]]s. Full tag was used for 512 or less [[KiB]] memory and partial tag for larger caches.
 
 
 
* TLB
 
** ITLB
 
*** 24-entry, dual-port
 
** DTLB
 
*** 32-entry, dual-port
 
** STLB
 
*** 256-entry
 
 
 
Both AMD's and Intel's original models did not feature on-die L2$. When compared to [[Intel]]'s original {{intel|Pentium III}} L1 which was 32 KiB (albeit at higher associativity), K7 had superior performance due to having 4 times as much cache. By the following year AMD moved the cach on-die. With the introduction of the {{intel|Coppermine}} models, Intel moved the L2$ on-die as well with half of K7's latency. This change allowed Pentium models to outperform Athlon for certain workloads.
 
  
 
== Die Shot ==
 
== Die Shot ==
 
+
{{empty section}}
=== Duron DHD1200AMT1B ===
 
AMD {{amd|Duron}} {{amd|DHD1200AMT1B}} {{amd|Morgan|l=core}}-based core:
 
 
 
:[[File:AMD_DHD1200AMT1B_die_shot 2.jpg|650px]]
 
 
 
=== Athlon K7500MTR51B C ===
 
AMD {{amd|Athlon}} {{amd|K7500MTR51B C}} {{amd|Argon|l=core}}-based core:
 
 
 
:[[File:AMD Athlon K7500MTR51B C die shot.jpg|650px]]
 
  
 
== All K7 Chips ==
 
== All K7 Chips ==
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<tr><th colspan="8" style="background:#D6D6FF;">K7 Chips</th></tr>
 
<tr><th colspan="8" style="background:#D6D6FF;">K7 Chips</th></tr>
 
<tr><th>Model</th><th>Family</th><th>Core</th><th>Launched</th><th>TDP</th><th>V<sub>CORE</sub></th><th>Freq</th><th>Max Mem</th></tr>
 
<tr><th>Model</th><th>Family</th><th>Core</th><th>Launched</th><th>TDP</th><th>V<sub>CORE</sub></th><th>Freq</th><th>Max Mem</th></tr>
{{table sep|col=8|[[Uniprocessors]]}}
+
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::K7]]
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::K7]] [[max cpu count::1]]
 
|?full page name
 
|?model number
 
|?microprocessor family
 
|?core name
 
|?first launched
 
|?tdp#W
 
|?core voltage#V
 
|?base frequency#MHz
 
|?max memory#GB
 
|format=template
 
|template=proc table 2
 
|searchlabel=
 
|userparam=9
 
|mainlabel=-
 
}}
 
{{table sep|col=8|[[Uniprocessors]]}}
 
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::K7]] [[max cpu count::!1]]
 
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number

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codenameK7 +
core count1 +
designerAMD +
first launchedJune 23, 1999 +
full page nameamd/microarchitectures/k7 +
instance ofmicroarchitecture +
instruction set architecturex86-32 +
manufacturerAMD +
microarchitecture typeCPU +
nameK7 +
pipeline stages (max)15 +
pipeline stages (min)10 +
process250 nm (0.25 μm, 2.5e-4 mm) +, 180 nm (0.18 μm, 1.8e-4 mm) + and 130 nm (0.13 μm, 1.3e-4 mm) +