Editing amd/cores/rome

{{amd title|Rome|core}}
{{core
|name=Rome
|no image=No
|developer=AMD
|manufacturer=TSMC
|manufacturer 2=GlobalFoundries
|first announced=May 16, 2017
|isa=x86-64
|microarch=Zen 2
|word=64 bit
|proc=14 nm
|tech=CMOS
|package name 1=amd,socket_sp3
|predecessor=Naples
|predecessor link=amd/cores/naples
|successor=Milan
|successor link=amd/cores/milan
|proc 2=7 nm
}}
'''Rome''' codename for [[AMD]]'s high-performance enterprise-level server [[multiprocessors]] based on the {{amd|Zen 2|l=arch}} microarchitecture serving as a successor to {{\\|Naples}}. Rome-based chips are fabricated on TSMC [[7 nm process]] with some components made on GlobalFoundries [[14 nm process]].

[[File:amd epyc rodmap.png|right|thumb|AMD datacenter roadmap]]

== Overview ==
AMD Rome [[system on chips]] are a series of high-performance [[multiprocessors]] designed by [[AMD]] based on their {{amd|Zen 2|l=arch}} microarchitecture. Rome SoCs support both single and 2-way multiprocessing with up to a maximum of 64 cores (and 128 threads) per processor for a total of up to 128 cores (and 256 threads) for a 2-way MP system. Those SoCs sports 128 PCIe lanes each, however, half of them are lost when in 2-way MP (leaving the system with the same overall lanes count as a single socket solution). Communication between the two chips is done via AMD's {{amd|Infinity Fabric}} protocol over the 64 reserved lanes. Rome is backwards platform/socket compatible with Naples and forward-compatible with Milan.

=== Common Features ===
All Naples processors have the following:
* 128 PCIe lanes (in both single-way and dual-way multiprocessing)
** PCIe Gen 4
* Octa-channel Memory
** Up to DDR4-2666 ECC
** Up to 4 [[TiB]] (8 TiB in 2MP)
* Up to 64 cores / 128 threads
* Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}}

== Rome Processors ==
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           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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{{comp table start}}
<table class="comptable sortable tc5 tc6">
{{comp table header|main|10:List of Rome Processors}}
{{comp table header|cols|Family|Price|Launched|Cores|Threads|TDP|L2$|L3$|Base|Turbo}}
{{#ask: [[Category:microprocessor models by amd]] [[core name::Rome]]
 |?full page name
 |?model number
 |?microprocessor family
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |format=template
 |template=proc table 3
 |userparam=12
 |mainlabel=-
 |valuesep=,
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Rome]]}}
</table>
{{comp table end}}

== See also ==
{{amd zen 2 core see also}}
back image	+
designer	AMD +
first announced	May 16, 2017 +
first launched	August 7, 2019 +
instance of	core +
isa	x86-64 +
isa family	x86 +
main image	+
main image caption	Package front +
manufacturer	TSMC + and GlobalFoundries +
microarchitecture	Zen 2 +
name	Rome +
package	FCLGA-4094 + and SP3 +
process	7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
socket	LGA-4094 + and SP3 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +