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| | {{amd title|Rome|core}} | | {{amd title|Rome|core}} |
| | {{core | | {{core |
| − | |name=Rome | + | | name = Rome |
| − | |image=amd rome (front).jpg | + | | image = |
| − | |caption=Package front | + | | image size = |
| − | |back image=amd rome (back).jpg | + | | image 2 = |
| − | |back image size=Package back | + | | image 2 size = |
| − | |developer=AMD | + | | developer = AMD |
| − | |manufacturer=TSMC | + | | manufacturer = GlobalFoundries |
| − | |manufacturer 2=GlobalFoundries
| + | | first announced = May 16, 2017 |
| − | |first announced=May 16, 2017 | + | | first launched = |
| − | |first launched=August 7, 2019 | + | | isa = x86-64 |
| − | |isa=x86-64 | + | | microarch = Zen 2 |
| − | |isa family=x86
| + | | word = 64 bit |
| − | |microarch=Zen 2 | + | | proc = 7 nm |
| − | |word=64 bit | + | | tech = CMOS |
| − | |proc=7 nm | + | | clock min = |
| − | |tech=CMOS | + | | clock max = |
| − | |package name 1=amd,socket_sp3 | + | | package = |
| − | |predecessor=Naples
| + | | socket = |
| − | |predecessor link=amd/cores/naples | |
| − | |successor=Milan | |
| − | |successor link=amd/cores/milan | |
| − | |proc 2=14 nm
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| − | }}
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| − | '''Rome''' is codename for [[AMD]]'s high-performance server microprocessors based on the {{amd|Zen 2|l=arch}} microarchitecture serving as a successor to {{\\|Naples}}.
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| − | | |
| − | Rome-based microprocessors are branded as second-generation, {{amd|EPYC#7002 Series (Zen 2)|7002-series}}, {{amd|EPYC|EPYC processors}}.
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| − | | |
| − | [[File:amd epyc rodmap.png|right|thumb|AMD datacenter roadmap]]
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| − | | |
| − | == Overview ==
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| − | AMD Rome [[system on chips]] are a series of high-performance [[multiprocessors]] designed by [[AMD]] based on their {{amd|Zen 2|l=arch}} microarchitecture. Rome-based logic chips are fabricated on TSMC [[7 nm process]] with the i/o components made on GlobalFoundries [[14 nm process]]. Rome SoCs support both single and 2-way multiprocessing with up to a maximum of 64 cores (and 128 threads) per processor for a total of up to 128 cores (and 256 threads) for a 2-way MP system. Those SoCs support 128 PCIe lanes each. When in a two-socket configuration, a total of 160 PCIe lanes can be provided at the platform level by both chips. Rome is backward platform/socket (Socket SP3) compatible with {{\\|Naples}} and forward-compatible with {{\\|Milan}}.
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| | | | |
| − | === Common Features ===
| + | | succession = Yes |
| − | All Rome processors have the following:
| + | | predecessor = Naples |
| − | * 128 PCIe lanes (in both single-way and dual-way multiprocessing)
| + | | predecessor link = amd/cores/naples |
| − | ** PCIe Gen 4
| + | | successor = Milan |
| − | * Octa-channel Memory
| + | | successor link = amd/cores/mila |
| − | ** Up to DDR4-3200 ECC
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| − | ** Up to 4 [[TiB]]
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| − | *** Up to 16 x 256 GiB @ 1.2 V
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| − | *** RDIMM/LRDIMM/3DS/NVDIMM
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| − | * Up to 64 cores / 128 threads
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| − | * Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}}
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| − | | |
| − | {{clear}}
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| − | | |
| − | == Rome Processors ==
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| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − | | |
| − | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc5 tc6">
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| − | {{comp table header|main|10:List of Rome Processors}}
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| − | {{comp table header|cols|Family|Price|Launched|Cores|Threads|TDP|L2$|L3$|Base|Turbo}}
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| − | {{comp table header|lsep|25:[[Uniprocessors]]}}
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| − | {{#ask: [[Category:microprocessor models by amd]] [[core name::Rome]] [[max cpu count::1]]
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| − | |?full page name
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| − | |?model number
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| − | |?microprocessor family
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| − | |?release price
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| − | |?first launched
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| − | |?core count
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| − | |?thread count
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| − | |?tdp
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| − | |?l2$ size
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| − | |?l3$ size
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| − | |?base frequency#GHz
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| − | |?turbo frequency#GHz
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| − | |format=template
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| − | |template=proc table 3
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| − | |userparam=12
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| − | |mainlabel=-
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| − | |valuesep=,
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| | }} | | }} |
| − | {{comp table header|lsep|25:[[Multiprocessors]] (dual-socket)}}
| + | '''Rome''' is the codename for [[AMD]]'s high-performance enterprise-level server [[multiprocessors]] based on the {{amd|Zen 2|l=arch}} microarchitecture serving as a successor to {{\\|Naples}}. Rome-based chips are set to be fabricated on GlobalFoundries' [[7 nm process]]. |
| − | {{#ask: [[Category:microprocessor models by amd]] [[core name::Rome]] [[max cpu count::>>1]]
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| − | |?full page name
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| − | |?model number
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| − | |?microprocessor family
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| − | |?release price
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| − | |?first launched
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| − | |?core count
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| − | |?thread count
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| − | |?tdp
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| − | |?l2$ size
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| − | |?l3$ size
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| − | |?base frequency#GHz
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| − | |?turbo frequency#GHz
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| − | |format=template
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| − | |template=proc table 3
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| − | |userparam=12
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| − | |mainlabel=-
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| − | |valuesep=,
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| − | }}
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| − | {{comp table header|lsep|25:HPC-optimized SKUs}}
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| − | {{#ask: [[Category:microprocessor models by amd]] [[core name::Rome]] [[part of::HPC-optimized SKUs]]
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| − | |?full page name
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| − | |?model number
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| − | |?microprocessor family
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| − | |?release price
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| − | |?first launched
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| − | |?core count
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| − | |?thread count
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| − | |?tdp
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| − | |?l2$ size
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| − | |?l3$ size
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| − | |?base frequency#GHz
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| − | |?turbo frequency#GHz
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| − | |format=template
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| − | |template=proc table 3
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| − | |userparam=12
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| − | |mainlabel=-
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| − | |valuesep=,
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| − | }}
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| − | {{comp table header|lsep|25:Frequency-optimized SKUs}} | |
| − | {{#ask: [[Category:microprocessor models by amd]] [[core name::Rome]] [[part of::Frequency-optimized SKUs]]
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| − | |?full page name
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| − | |?model number
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| − | |?microprocessor family
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| − | |?release price
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| − | |?first launched
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| − | |?core count
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| − | |?thread count
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| − | |?tdp
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| − | |?l2$ size
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| − | |?l3$ size
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| − | |?base frequency#GHz
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| − | |?turbo frequency#GHz
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| − | |format=template
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| − | |template=proc table 3
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| − | |userparam=12
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| − | |mainlabel=-
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| − | |valuesep=,
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| − | }} | |
| − | {{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Rome]]}}
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| − | </table>
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| − | {{comp table end}}
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| − | | |
| − | === SKU Comparison ===
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| − | Below are a number of SKU comparison graphs based on their specifications.
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| − | | |
| − | <div style="float: left; margin: 10px">
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| − | {{#ask: [[Category:microprocessor models by amd]] [[core name::Rome]] | |
| − | |?core count
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| − | |?base frequency
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| − | |charttitle=Cores vs. Base Frequency
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| − | |numbersaxislabel=Frequency (MHz)
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| − | |labelaxislabel=Core Count
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| − | |height=400
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| − | |width=400
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| − | |theme=vector
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| − | |group=property
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| − | |grouplabel=subject
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| − | |charttype=scatter
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| − | |format=jqplotseries
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| − | |mainlabel=-
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| − | }} | |
| − | </div>
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| − | | |
| − | <div style="float: left; margin: 10px">
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| − | {{#ask: [[Category:microprocessor models by amd]] [[core name::Rome]]
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| − | |?core count
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| − | |?turbo frequency
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| − | |charttitle=Cores vs. Turbo Frequency
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| − | |numbersaxislabel=Frequency (MHz)
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| − | |labelaxislabel=Core Count
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| − | |height=400
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| − | |width=400
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| − | |theme=vector
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| − | |group=property
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| − | |grouplabel=subject
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| − | |charttype=scatter
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| − | |format=jqplotseries
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| − | |mainlabel=-
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| − | }}
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| − | </div>
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| − | | |
| − | <div style="float: left; margin: 10px">
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| − | {{#ask: [[Category:microprocessor models by amd]] [[core name::Rome]]
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| − | |?core count
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| − | |?tdp
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| − | |charttitle=Cores vs. TDP
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| − | |numbersaxislabel=TDP (W)
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| − | |labelaxislabel=Core Count
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| − | |height=400
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| − | |width=400
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| − | |theme=vector
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| − | |group=property
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| − | |grouplabel=subject
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| − | |charttype=scatter
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| − | |format=jqplotseries
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| − | |mainlabel=-
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| − | }}
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| − | </div>
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| − | | |
| − | <div style="float: left; margin: 10px">
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| − | {{#ask: [[Category:microprocessor models by amd]] [[core name::Rome]]
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| − | |?turbo frequency
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| − | |?tdp
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| − | |charttitle=Frequency vs. TDP
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| − | |numbersaxislabel=TDP (W)
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| − | |labelaxislabel=Frequency (MHz)
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| − | |height=400
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| − | |width=400
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| − | |theme=vector
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| − | |group=property
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| − | |grouplabel=subject
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| − | |charttype=scatter
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| − | |format=jqplotseries
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| − | |mainlabel=-
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| − | }}
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| − | </div>
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| − | | |
| − | {{clear}}
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| − | | |
| − | == See also ==
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| − | {{amd zen 2 core see also}}
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