Semiconductor & Computer Engineering
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Difference between revisions of "ambric/am2000/am2035"
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Revision as of 18:05, 24 June 2016
Template:mpu Am2035 was an MPPA introduced in late 2006 by Ambric. This model was made of 35 Brics arranged as a grid, making up a total of 280 32-bit RICS-like cores operating asynchronously at 1-333 MHz.
Architecture
- Main article: Am2000 § Architecture
The Am2035 is made of 35 homogeneous 'Brics' laid out in a grid to form 280 cores and 280 RAM units.
General layout:
- 35x Brics
Cache
The Am2035 contains 35 Brics, each with its own RAM Unit (RU) of 13 kB of SRAM for a total of 455 kB of SRAM.
Memory controller
| Integrated Memory Controller | |
| Type | DDR2-400 |
| Controllers | 2 |
| Channels | 1 |
| Max memory | 4 GB |
Expansions
- PCIe
- JTAG
- GPIO @ 100 MHz
- serial flash
Facts about "Am2035 - Ambric"
| base frequency | 333 MHz (0.333 GHz, 333,000 kHz) + |
| bus speed | 100 MHz (0.1 GHz, 100,000 kHz) + |
| clock multiplier | 3.3 + |
| core count | 280 + |
| designer | Ambric + |
| family | Am2000 + |
| first announced | October 10, 2006 + |
| first launched | January 2007 + |
| full page name | ambric/am2000/am2035 + |
| has feature | PCIe +, JTAG +, GPIO + and serial flash + |
| has locked clock multiplier | false + |
| instance of | microprocessor + |
| last order | 2012 + |
| last shipment | 2012 + |
| ldate | January 2007 + |
| market segment | Embedded + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| microarchitecture | Ambric + |
| model number | Am2035 + |
| name | Am2035 + |
| part number | Am2035 + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| series | Gen 1 + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + |
