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{{ambric title|Am2024}}
 
{{ambric title|Am2024}}
{{mpu
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{{chip
 
| name                = Am2024
 
| name                = Am2024
 
| no image            = Yes
 
| no image            = Yes
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| frequency          = 333 MHz
 
| frequency          = 333 MHz
 
| bus type            =  
 
| bus type            =  
| bus speed          =  
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| bus speed          = 100 MHz
 
| bus rate            =  
 
| bus rate            =  
| clock multiplier    =  
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| clock multiplier    = 3.3
  
 
| microarch          = Ambric  
 
| microarch          = Ambric  
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| thread count        =  
 
| thread count        =  
 
| max cpus            =  
 
| max cpus            =  
| max memory          =  
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| max memory          = 4 GiB
  
 
| electrical          =  
 
| electrical          =  
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| socket 0 type      =  
 
| socket 0 type      =  
 
}}
 
}}
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'''Am2024''' was an [[MPPA]] introduced in late 2006 by [[Ambric]]. This model was made of {{ambric|am2000#Architecture|24 Brics}} arranged as a grid, making up a total of 192 {{arch|32}} [[RICS]]-like cores operating asynchronously at 1-333 MHz.
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== Architecture ==
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{{main|ambric/am2000#Architecture|l1=Am2000 § Architecture}}
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The Am2024 is made of 24 homogeneous 'Brics' laid out in a grid to form 192 cores and 192 RAM units.
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General layout:
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* 24x Brics
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** 2x Computer Unit (CU)
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*** 2x SRD {{arch|32}} CPU
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*** 2x RD {{arch|32}} CPU
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** 2x [[RAM]] Unit (RU)
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*** 4x 2 KB [[SRAM]] bank
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== Cache ==
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The Am2035 contains 24 Brics, each with its own [[RAM]] Unit (RU) of 13 kB of SRAM for a total of 312 kB of SRAM.
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== Memory controller ==
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{{integrated memory controller
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| type              = DDR2-400
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| controllers        = 2
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| channels          = 1
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| ecc support        =
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| max bandwidth      =
 +
| bandwidth schan    =
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| bandwidth dchan    =
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| max memory        = 4 GiB
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}}
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== Expansions ==
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* [[has feature::PCIe]]
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* [[has feature::JTAG]]
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* [[has feature::GPIO]] @ 100 MHz
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* [[has feature::serial flash]]

Latest revision as of 15:16, 13 December 2017

Edit Values
Am2024
General Info
DesignerAmbric
Model NumberAm2024
Part NumberAm2024
MarketEmbedded
IntroductionOctober 10, 2006 (announced)
January 2007 (launched)
End-of-life2012 (last order)
2012 (last shipment)
General Specs
FamilyAm2000
SeriesGen 1
LockedNo
Frequency333 MHz
Bus speed100 MHz
Clock multiplier3.3
Microarchitecture
MicroarchitectureAmbric
Process130 nm
TechnologyCMOS
Word Size32 bit
Cores192
Max Memory4 GiB

Am2024 was an MPPA introduced in late 2006 by Ambric. This model was made of 24 Brics arranged as a grid, making up a total of 192 32-bit RICS-like cores operating asynchronously at 1-333 MHz.

Architecture[edit]

Main article: Am2000 § Architecture

The Am2024 is made of 24 homogeneous 'Brics' laid out in a grid to form 192 cores and 192 RAM units.

General layout:

  • 24x Brics

Cache[edit]

The Am2035 contains 24 Brics, each with its own RAM Unit (RU) of 13 kB of SRAM for a total of 312 kB of SRAM.

Memory controller[edit]

Integrated Memory Controller
Type DDR2-400
Controllers 2
Channels 1
Max memory 4 GiB

Expansions[edit]

  • PCIe
  • JTAG
  • GPIO @ 100 MHz
  • serial flash
Facts about "Am2024 - Ambric"
base frequency333 MHz (0.333 GHz, 333,000 kHz) +
bus speed100 MHz (0.1 GHz, 100,000 kHz) +
clock multiplier3.3 +
core count192 +
designerAmbric +
familyAm2000 +
first announcedOctober 10, 2006 +
first launchedJanuary 2007 +
full page nameambric/am2000/am2024 +
has featurePCIe +, JTAG +, GPIO + and serial flash +
has locked clock multiplierfalse +
instance ofmicroprocessor +
last order2012 +
last shipment2012 +
ldateJanuary 2007 +
market segmentEmbedded +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
microarchitectureAmbric +
model numberAm2024 +
nameAm2024 +
part numberAm2024 +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesGen 1 +
technologyCMOS +
word size32 bit (4 octets, 8 nibbles) +