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- {{intel title|Silvermont|arch}} | designer = Intel9 KB (1,160 words) - 09:35, 25 September 2019
- {{intel title|Sandy Bridge (client)|arch}} |designer=Intel84 KB (13,075 words) - 00:54, 29 December 2020
- {{intel title|Skylake (client)|arch}} |designer=Intel79 KB (11,922 words) - 06:46, 11 November 2022
- {{intel title|Kaby Lake|arch}} |designer=Intel38 KB (5,431 words) - 10:41, 8 April 2024
- {{intel title|Ice Lake (client)|arch}} |designer=Intel23 KB (3,613 words) - 12:31, 20 June 2021
- {{intel title|Coffee Lake|arch}} |designer=Intel30 KB (4,192 words) - 13:48, 10 December 2023
- {{intel title|Gen9|arch}} | designer = Intel33 KB (4,255 words) - 17:41, 1 November 2018
- {{intel title|Skylake (server)|arch}} |designer=Intel52 KB (7,651 words) - 00:59, 6 July 2022
- ...age regulator|regulates]] and down steps [[voltage]] from its input (e.g., system [[power rail]]) to its output (e.g., integrated circuits). In the context o In a modern computer system, the typical motherboard VRM might have 3 or more phases. A multi-phase VRM18 KB (3,026 words) - 16:55, 19 January 2020
- {{intel title|Mesh Interconnect Architecture}} ...imensional array of half rings. Their mesh architecture has replaced the {{intel|ring interconnect architecture}} in the server and [[HPC]] markets.7 KB (1,071 words) - 12:59, 2 November 2021
- {{intel title|Raptor Lake|arch}} |designer=Intel9 KB (1,220 words) - 00:23, 17 January 2023