• rockwell international/pps-4
  ...p microcomputer) was actually a [[microcontroller]], including the program memory internally.
  3 KB (359 words) - 17:26, 19 May 2016
• motorola/mc14500
  | {{motorola|MCM7641}} || Program Counter ...as done externally, in theory at least, this MPU can support any amount of memory needed.
  4 KB (538 words) - 10:44, 22 May 2018
• rockwell international/pps-4-1
  ...ockwell|PPS-4/2}} with the addition of a [[clock generator]] and [[program memory]] incorporated internally, making it a single-chip system (hence the "/1").
  2 KB (219 words) - 01:00, 19 May 2016
• amd/am29100
  ...29112}} [[microsequencer]] or custom logic) to handle [[subroutines]], and memory access.
  3 KB (323 words) - 11:26, 15 August 2017
• intel/mcs-8/isa
  | format = Register-Memory ...n operation. Multi-byte instructions must be stored in successive order in memory. Typical operations involving register-register operations such as arithmet
  13 KB (2,079 words) - 09:11, 29 September 2019
• intel/mcs-8/8008
  |max memory=16 KiB ...500 kHZ, had 8-bit data words, and could address 16KB of memory (14-bits [[program counter|PC]]). Originally commissioned by [[Datapoint Corporation]] (then C
  2 KB (254 words) - 19:24, 23 March 2022
• intel/microarchitectures/skylake (client)
  ** Memory Subsystem * Memory
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/core i5
  |?has ecc memory support |?has ecc memory support
  34 KB (4,663 words) - 20:38, 20 February 2023
• amd/am486
  |?max memory#GB |?max memory#GB
  13 KB (1,897 words) - 09:30, 21 July 2021
• mathstar/builder
  ...(MAC), and [[Register File]] (RF). The control program guides the overall program execution and the datapath setup. Datapath is {{arch|16}} but may be combin ...l !! Objects !! Parallel I/O Inter. !! Serial I/O Trans. !! GPIO !! 36-bit Memory Cntr
  5 KB (596 words) - 21:23, 19 November 2017
• amd/microarchitectures/zen
  === Memory Hierarchy === ...n all four areas of the core (the front end, the execution engine, and the memory subsystem) as well as Zen's new [[SoC]] CCX (CPU Complex) modular design. T
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  ** Memory subsystem * <code>{{x86|MCOMMIT}}</code> - Commit stores to memory
  57 KB (8,701 words) - 22:11, 9 October 2022
• acorn/microarchitectures/arm1
  ...simplify system design, these clocks may be stretched to work in-sync with memory access times. ...he address register gets sent through the address pins and is fetched from memory.
  12 KB (1,886 words) - 12:56, 14 January 2021
• arm/26-bit architectures
  ...unter]] was 24 bits allowing for a 26-bit address space of up to 64 MiB of memory. The other bits were used for the {{arm|Processor Status Register}}. With t ...raise a memory access exception. On the {{arm|32-bit architectures}}, the program counter was extended to 30 bits, allowing the full 4 GiB address space to b
  3 KB (535 words) - 09:13, 18 February 2021
• arm/armv1
  ...[[program counter]] allowing for a 26-bit address space of up to 64 MiB of memory. ...oad Instructions'''</span><br><small>Load instructions move the content of memory addresses into registers.</small>}}
  10 KB (1,558 words) - 15:07, 2 July 2017
• acorn/microarchitectures/arm2
  ...ements. The ARM2 was capable of exceeding 10 MIPS when not bottlenecked by memory with an average of around 6 MIPS. Unlike the ARM1 which was predominantly a * > 2x MIPS when not bottlenecked by memory
  14 KB (2,093 words) - 04:42, 10 July 2018
• arm holdings/microarchitectures/arm6
  ** Can map 4 GiB of memory ** {{arm|CPSR}} & {{arm|SPSR}} moved out of the [[program counter]]
  11 KB (1,679 words) - 18:49, 18 May 2023
• intel/microarchitectures/skylake (server)
  ** Memory Subsystem * Memory
  52 KB (7,651 words) - 00:59, 6 July 2022
• intel/cores/coffee lake h
  * Dual-channel Memory |?has ecc memory support
  5 KB (648 words) - 17:43, 6 December 2018
• bitmain/sophon/bm1680
  |max memory=16 GiB The chip consists of five subsystems: [[NPU]], [[MCU]], Chip Link, Memory, and Peripherals.
  4 KB (603 words) - 09:59, 11 August 2018

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