• amd/athlon mp
  ...ng an effective 266 MT/s transfer rate (note that 'B' models operated at a lower FSB of 100 MHz). These processors support {{x86|MMX}}, {{x86|SSE}}, {{x86|E ...r price than the newer Opteron models which made them attractive for entry-level servers and workstations. These processors support {{x86|MMX}}, {{x86|SSE}}
  11 KB (1,571 words) - 18:57, 17 November 2016
• mediatek/helio/mt6797
  ...except for the lower clocked {{armh|Cortex-A72|A72|l=arch}} cores and the lower clocked GPU. ...esigned is composed of 3 individual clusters of CPU cores depending on the level of performance required by the active applications.
  6 KB (713 words) - 21:16, 2 May 2021
• amd/ryzen 7
  ...high-end {{intel|Core i7}} processors, offering competitive performance at lower prices.
  15 KB (2,095 words) - 12:18, 2 October 2022
• amd/epyc
  ...<table style="text-align:left"><th colspan="2">Product Model / Performance Level</th> ...g a 32 MiB L3 cache, i.e. twice as much L3 cache available to one core and lower inter-core latency.
  19 KB (2,580 words) - 02:46, 23 November 2022
• amd/cores/milan
  ...|EPYC 7001}} "{{\\|Naples}}" series CPUs. "Type-0" boards designed for the lower memory and PCIe bus frequencies of "Naples" processors are not supported.<r ...still supports the ''NUMA Nodes Per Socket'' (NPS) and ''<abbr title="Last Level Cache">LLC</abbr>/L3/CCX as NUMA domain'' BIOS setup options. 6-way memory
  19 KB (2,734 words) - 01:26, 31 May 2021
• intel/microarchitectures/skylake (server)
  ...).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || [[6 cores|6]] - [[8 cores|8]] || {{tchk ...ver}} || style="text-align: left;" | Mid-range performance / <br>Efficient lower power || [[4 cores|4]] - [[12 cores|12]] || {{tchk|yes}} || {{tchk|yes}} ||
  52 KB (7,651 words) - 00:59, 6 July 2022
• intel/upgrade service
  ...ntel|Pentium (2009)|Pentium}} models would be at roughly {{intel|Core i3}} level and the Core i3 would be at roughly the low-end {{intel|Core i5}} models.
  4 KB (545 words) - 12:49, 18 July 2020
• microsoft/scorpio engine
  ...transfer of 6800 MT/s. The bandwidth increase has effectively reached the level of a discrete graphics card and almost 1.5x the bandwidth of the PS4 Pro (w ...us for a total bus width of 3,072-bit. The 12 channels allow the system to lower the granularity of memory accesses while the wide bus allows the system to
  15 KB (2,390 words) - 02:54, 17 May 2023
• amd/microarchitectures/zen+
  *** Lower Power Zen TLB consists of dedicated level one TLB for instruction cache and another one for data cache.
  11 KB (1,613 words) - 08:39, 3 March 2024
• mirc/identifiers/$findfile
  ...'' - optional folder depth, counting DIR as the first level. 0 or 1 is DIR level only. If depth not used, there's no depth limit. echoes all filenames in c:\program files\ and 1 level beneath it. .shortfn causes all foldernames and pathnames to be converted t
  5 KB (759 words) - 07:46, 15 December 2019
• intel/microarchitectures/cascade lake
  ...).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || 6 || {{tchk|no}} || {{tchk|no}} || {{tc ...ver}} || style="text-align: left;" | Mid-range performance / <br>Efficient lower power || 8-16 || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 1 || 2 ||
  32 KB (4,535 words) - 05:44, 9 October 2022
• mirc/identifiers/$hash
  ...h(parameter,32) with $crc(parameter,0). While $crc does not provide crypto level ability to make it difficult to create collisions, it does have the propert If the hash needs to be based on a crypto-level hash, or needs more than 32 bits, use up-to-52 bits from $sha1 or $sha512 i
  13 KB (2,030 words) - 14:28, 5 February 2023
• samsung/microarchitectures/m3
  *** New mid-level DTLB *** 512-entry Mid-level DTLB
  20 KB (3,149 words) - 10:44, 15 February 2020
• amd/packages/socket sp3
  :* SATA Gen 1, 2, 3 (6&nbsp;Gb/s) protocol supported on the lower 8 lanes of P0, P1, G2, G3 ...ng potentially bad data. In other words this historic term refers to a low-level fatal error signal. The condition is passed on through the Data Fabric and
  110 KB (21,122 words) - 02:46, 13 March 2023
• arm holdings/microarchitectures/cortex-a76
  ...2}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A55}}) in a {{armh|DynamIQ big.LITTLE}} confi ...6 is a 4-way superscalar out-of-order processor with a private level 1 and level 2 caches. It is designed to be implemented inside the [[DynamIQ Shared Unit
  14 KB (2,183 words) - 17:15, 17 October 2020
• arm holdings/microarchitectures/cortex-a77
  *** lower latency recovery from branch mispredict flushes ...of-order processor with a 12-wide execution engine, a private level 1, and level 2 caches. It is designed to be implemented inside the [[DynamIQ Shared Unit
  17 KB (2,555 words) - 06:08, 16 June 2023
• nvidia/microarchitectures/nvdla
  ...pported. NVDLA primarily targets edge devices, IoT applications, and other lower-power inference designs. At a high level, NVDLA stores both the activation and the inputs in a convolutional [[buffe
  5 KB (713 words) - 18:16, 1 September 2022
• nanotube-ram
  ...ctrostatic force is used to combine a sufficiently large amount of CNTs to lower the resistance and an opposite force is used to break them apart to signifi ...void and increase the resistance and are then forced back down in order to lower the resistance. Both the length and the diameter of the carbon nanotubes is
  6 KB (1,010 words) - 02:42, 31 January 2019
• arm/aarch64
  ...hanism found in {{\\|AArch32}} was not necessary because, at any exception level, it's now possible to simply use the dedicated stack pointer. Additionally, Each exception level except for EL0 has its own [[interrupt vector table|vector table]]. The vec
  4 KB (661 words) - 20:26, 2 May 2019
• brain floating-point format
  ...worth it for Google and their {{google|TPU}} implementation. At the system level, the benefits in memory capacity saving and bandwidth can also be realized ...s those of float32. Since bfloat16 maintains the same dynamic range, using lower precisions works well with bfloat16 without loss scaling. Getting training
  4 KB (582 words) - 12:35, 26 April 2021

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