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  • ...l keeping everything closely tied together with respect to the [[back-side bus]]. The separate (slower) cache die also meant the processor was cheaper to This table is generated automatically from the data in the actual articles.
    5 KB (635 words) - 09:54, 11 November 2017
  • ! Model !! Introduction !! Ext. Bus !! Frequency !! Notes ! Model !! Introduction !! Ext. Bus !! Frequency !! Notes
    4 KB (400 words) - 08:43, 5 December 2022
  • ...tly used data and instructions. Various enhancements were also made to the bus interface including faster communication that required single clock cycle i This table is generated automatically from the data in the actual articles.
    8 KB (953 words) - 08:27, 29 October 2022
  • | bus type = FSB | bus speed = 33 MHz
    2 KB (214 words) - 16:13, 13 December 2017
  • ...essors are [[dual-core]] processors. These processors had the [[front-side bus|FSB]] replaced with {{intel|Direct Media Interface}} 1.0. These processors This table is generated automatically from the data in the actual articles.
    25 KB (3,397 words) - 03:12, 3 October 2022
  • ...essors are [[dual-core]] processors. These processors had the [[front-side bus|FSB]] replaced with {{intel|Direct Media Interface}} 1.0 and introduced {{x * '''Bus:''' {{intel|DMI}} (2.5 GT/s) interface
    34 KB (4,663 words) - 20:38, 20 February 2023
  • ...versions introduced had lower clock frequency which matched their external bus speed. Later versions introduced a [[clock multiplier]]: DX2 having a multi This table is generated automatically from the data in the actual articles.
    13 KB (1,897 words) - 09:30, 21 July 2021
  • ...nce comparable to the Pentium-75. The clock multiplier was set to x4 (e.g. bus speed of 33 MHz would have a core frequency of 133 MHz). Essentially, one c This table is generated automatically from the data in the actual articles.
    7 KB (1,043 words) - 16:50, 14 June 2020
  • This table is generated automatically from the data in the actual articles. <tr><th>Model</th><th>Launched</th><th>Process</th><th>Freq</th><th>Bus</th><th>Max Mem</th><th>Package</th><th>Power</th><th>Min T<sub>case</sub><
    9 KB (1,192 words) - 01:35, 29 May 2016
  • ...amd|Am286#Low-power CMOS models|from the Am286 family}} and incorporated a bus controller, DMA controller, interrupt controller, and clock generator. The This table is generated automatically from the data in the actual articles.
    5 KB (750 words) - 21:22, 24 May 2016
  • This table is generated automatically from the data in the actual articles. <tr><th>Model</th><th>Launched</th><th>Process</th><th>Freq</th><th>Bus</th><th>Max Mem</th><th>Package</th><th>Power</th><th>Min T<sub>case</sub><
    5 KB (602 words) - 18:20, 3 June 2016
  • This table is generated automatically from the data in the actual articles. <tr><th>Model</th><th>Launched</th><th>Freq</th><th>Bus</th><th>Max Mem</th><th>V<sub>CORE</sub><th>Package</th><th>Min T<sub>case<
    9 KB (1,276 words) - 16:07, 28 June 2016
  • ...herals such as [[High-Level Data Link Control]] (HDLC), [[Universal Serial Bus]] (USB), High-Speed [[UART]], and [[Synchronous Serial Interface]] (SSI). * Multiplexed and nonmultiplexed address/data bus
    7 KB (962 words) - 04:25, 22 June 2017
  • | bus type = | bus speed = 6.25 MHz
    4 KB (364 words) - 16:51, 30 June 2017
  • | bus type = | bus speed = 10 MHz
    3 KB (364 words) - 16:51, 30 June 2017
  • | bus type = | bus speed = 12.5 MHz
    4 KB (364 words) - 16:52, 30 June 2017
  • | bus type = | bus speed = 6.25 MHz
    4 KB (374 words) - 16:51, 30 June 2017
  • | bus type = | bus speed = 10 MHz
    4 KB (374 words) - 16:52, 30 June 2017
  • | bus type = | bus speed = 6.25 MHz
    3 KB (367 words) - 16:50, 30 June 2017
  • | bus type = | bus speed = 10 MHz
    3 KB (367 words) - 16:51, 30 June 2017

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