• greenwaves/gap8
  ...[[convolutional neural network]]s (CNN). The GAP8 is said to offer a peak performance of up to 200 MOPS at 1 mW and up to 10 GOPS at a few tens of mW, making it ...the rest of the system is in deep idle state. The microcontroller and the compute engines sit on two entirely decoupled power domains, consuming power sparin
  6 KB (981 words) - 14:11, 28 February 2018
• google/pixel visual core
  ...ic processor]] designed from the ground-up in order to deliver the highest performance at low power. ...relies equally on both hardware and software in order to achieve the high performance and efficiency by using TensorFlow for machine learning and Halide for imag
  4 KB (617 words) - 10:03, 19 April 2019
• intel/cores/cascade lake ap
  '''Cascade Lake AP''' ('''CLX-AP''', '''Cascade Lake Advanced Performance''') is code name for a series of high core-count multi-chip packaged server ...ased individually. Instead, they can only be bought as part of the S9200WK compute module (essentially a complete system designed by Intel).
  4 KB (612 words) - 18:46, 1 February 2020
• supercomputers/summit
  ...educed the number of nodes to only 4,608, but tenfold the peak theoretical performance from 27 petaFLOPS to around 225 PF. Summit has over 200 [[petaFLOPS]] of theoretical compute power and over 3 AI exaFLOPS for AI workloads.
  9 KB (1,496 words) - 20:39, 21 July 2019
• ccix
  ...16 GT/s and 25 GT/s per link with support for port aggregation for higher performance. ...te-Architectures-Availability ''CCIX™ Consortium Enables Next Generation Compute Architectures with the Availability of Base Specification 1.0''] [Press rel
  4 KB (614 words) - 09:54, 7 October 2018
• bitmain/sophon
  === High-performance === ...roprocessor models by bitmain]] [[family::Sophon]] [[market segment::!Edge Compute]]
  3 KB (413 words) - 12:02, 25 December 2018
• amd/packages/socket sp3
  ...AMD]] for the first three generations of their {{amd|EPYC}} family of high performance server processors. It supports eight channels of [[DDR4]] memory and eight ...layout, and schematic were published by the [https://opencompute.org Open Compute Project] under Project Olympus AMD EPYC, specifically the US1-EPYC implemen
  110 KB (21,122 words) - 02:46, 13 March 2023
• zhongshan subor/fireflight
  ...his chip can deliver 3.994 [[TFLOPS]] raw peak performance - about 66% the performance of the {{microsoft|Scorpio Engine}} (6 TFLOPS) and three times its predeces <tr><th>Peak Performance</th><td> ~4 TFLOPS (3,994,000,000,000 [[FLOPS]])</td></tr>
  4 KB (613 words) - 13:48, 12 May 2019
• supercomputers/astra
  ...rgy]] as part of a program that evaluates the feasibility of emerging high-performance computing architectures as production platforms to support NNSA's mission. ...CN9975]] processors with slightly over 1.2 MW power consumption for a peak performance of 2.322 [[petaFLOPS]]. Each [[ThunderX2 CN9975]] has [[28 cores]] operatin
  8 KB (1,133 words) - 23:36, 2 June 2020
• arm holdings/microarchitectures/neoverse n1
  '''Neoverse N1''' (codename '''Ares''') is a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server m ..., the Neoverse N1 is said to deliver a significant uplift in single-thread performance.
  7 KB (980 words) - 13:46, 18 February 2023
• flops
  ...ing-point operations per second''' ('''FLOPS''') is a measure of [[compute performance]] used to quantify the number of [[floating-point]] [[floating-point operat ...ing]] (e.g., [[supercomputers]]) in order to evaluate the peak theoretical performance of various scientific workloads. Traditionally, the FLOPS of a microprocess
  10 KB (1,204 words) - 15:03, 25 January 2023
• intel/configurable spatial accelerator
  ...t data graph execution]] architecture designed by [[Intel]] for the [[high-performance computing]] and [[data center]] markets. The CSA is designed to work alongs ...ng the traditional [[out-of-order]] [[superscalar]] while surpassing it in performance and power. CSA supports the same HPC programming models supported by tradit
  14 KB (2,130 words) - 20:19, 2 October 2018
• amd/cores/genoa
  .../1100/offering-unmatched-performance-leadership-energy "Offering Unmatched Performance, Leadership Energy Efficiency and Next-Generation Architecture, AMD Brings ...6 interfaces can be configured as cache-coherent {{wp|Compute Express Link|Compute Express Link}}. "Genoa" supports version 1.1 of the protocol, specifically
  14 KB (1,983 words) - 01:41, 2 April 2023
• nec/microarchitectures/sx-aurora
  ...successor to the {{\\|SX-ACE}}, a [[vector processor]] designed for [[high-performance]] scientific/research applications and supercomputers. The SX-Aurora deviat ...engine but a self-hosted accelerator, the SPU is designed to deliver high performance to keep pace with the VPU and other operating system-related tasks.
  16 KB (2,497 words) - 13:30, 15 May 2020
• bytes per flop
  ...mmon [[figure of merit]] in the [[HPC]] community used to analyze the peak performance of a system under [[memory-bound]] workloads.
  482 bytes (76 words) - 20:25, 23 November 2018
• qualcomm/snapdragon 800/8cx
  ...5 Silver]] high-efficiency cores operating at 1.8 GHz along with four high-performance [[Kryo 495 Gold]] operating at 2.84 GHz. The Snapdragon 8cx integrates the [[File:snapdragon-8cx-compute-platform-chip-on-wafer.jpg|thumb|right]]
  5 KB (597 words) - 20:19, 16 January 2022
• samsung/exynos/9820
  '''Exynos 9820''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in early ...ACs split between two execution cores. The new NPU is capable of a peaking compute of two teraOPS.
  5 KB (697 words) - 09:43, 28 April 2021
• bitmain/sophon/bm1880
  |market=Edge Compute ...chip is designed primarily for edge inference acceleration and has a peak performance of [[peak integer ops (8-bit)::2 TOPS]] (INT8) and a typical power consumpt
  2 KB (263 words) - 12:19, 25 December 2018
• intel/xeon platinum/9282
  '''Xeon Platinum 9282''' is a [[56-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 92 ...not be purchased independently and is only sold as part of Intel's S9200WK Compute Module.
  3 KB (553 words) - 04:34, 31 July 2022
• intel/xeon platinum/9242
  '''Xeon Platinum 9242''' is a [[48-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 92 ...not be purchased independently and is only sold as part of Intel's S9200WK Compute Module.
  3 KB (530 words) - 20:42, 3 April 2019

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)