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  • ...er [[integrated circuit]]s including [[flash memory]], [[network interface controller]]s, [[GPU]]s, [[chipset]]s, motherboards, and computers. * {{\\|Programmable Unified Memory Architecture}} (PUMA)
    9 KB (1,150 words) - 00:03, 2 October 2022
  • The '''COP400''' or '''COPS II''' or simply '''COPS''' ('''Controller Oriented Processor System II''') was a [[microprocessor family|family]] of ...rocontrollers, one of the earliest instances of multiple CPUs in on single integrated circuit.
    6 KB (685 words) - 22:49, 5 February 2016
  • | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
    4 KB (404 words) - 16:22, 13 December 2017
  • | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
    3 KB (401 words) - 14:24, 12 February 2019
  • | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
    3 KB (399 words) - 16:22, 13 December 2017
  • | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] called {{intel|Crystal Well}}.
    3 KB (400 words) - 16:22, 13 December 2017
  • | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
    3 KB (399 words) - 16:22, 13 December 2017
  • |max memory=32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
    3 KB (386 words) - 09:14, 26 December 2017
  • | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
    3 KB (401 words) - 16:22, 13 December 2017
  • | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
    3 KB (397 words) - 16:22, 13 December 2017
  • | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
    3 KB (398 words) - 16:22, 13 December 2017
  • | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
    4 KB (406 words) - 16:22, 13 December 2017
  • | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
    4 KB (404 words) - 16:19, 13 December 2017
  • | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
    3 KB (401 words) - 16:19, 13 December 2017
  • | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
    3 KB (396 words) - 16:22, 13 December 2017
  • | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
    3 KB (391 words) - 16:22, 13 December 2017
  • | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
    3 KB (399 words) - 16:27, 13 December 2017
  • |max memory=32 GiB ...Hz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
    4 KB (596 words) - 16:15, 13 December 2017
  • |max memory=32 GiB ...Hz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
    4 KB (596 words) - 16:15, 13 December 2017
  • |max memory=64 GiB ...of 1.05 GHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.
    4 KB (627 words) - 16:17, 13 December 2017
  • |max memory=64 GiB ...ency of 950 MHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 memory.
    4 KB (627 words) - 16:20, 13 December 2017
  • |max memory=32 GiB ...Hz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
    4 KB (640 words) - 02:21, 16 January 2019
  • |max memory=32 GiB ...Hz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
    4 KB (650 words) - 02:21, 16 January 2019
  • | max memory = 32 GiB | max memory addr =
    5 KB (469 words) - 16:22, 13 December 2017
  • | max memory = 32 GiB {{integrated graphic
    4 KB (407 words) - 16:22, 13 December 2017
  • | max memory = 32 GiB {{integrated graphic
    4 KB (401 words) - 16:22, 13 December 2017
  • | max memory = 32 GiB {{integrated graphic
    4 KB (395 words) - 16:22, 13 December 2017
  • | max memory = 32 GiB {{integrated graphic
    4 KB (424 words) - 16:22, 13 December 2017
  • | max memory = 32 GiB {{integrated graphic
    4 KB (405 words) - 16:22, 13 December 2017
  • |max memory=32 GiB {{integrated graphic
    4 KB (460 words) - 15:03, 24 March 2019
  • | max memory = 32 GiB {{integrated graphic
    4 KB (409 words) - 16:19, 13 December 2017
  • | max memory = 32 GiB {{integrated graphic
    4 KB (454 words) - 18:17, 2 November 2019
  • | max memory = 32 GiB {{integrated graphic
    4 KB (409 words) - 16:19, 13 December 2017
  • | max memory = 32 GiB {{integrated graphic
    4 KB (415 words) - 16:19, 13 December 2017
  • |max memory=32 GiB ...Hz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6167U comes with an additional 64 MiB of [[embedded DRAM]] side cache.
    4 KB (631 words) - 16:18, 13 December 2017
  • |max memory=32 GiB ...Hz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6287U comes with an additional 64 MiB of [[embedded DRAM]] side cache.
    4 KB (649 words) - 16:20, 13 December 2017
  • | max memory = 8 GiB == Memory controller ==
    3 KB (323 words) - 16:10, 13 December 2017
  • ...replace older relay-based [[ladder logic]] as a cheap [[programmable logic controller]]. Production continued well into the 1990s. ...esigned by Motorola. Intended to serve as a very simple programmable logic controller and replace and simplify older machinery, the MC14500 cheap price and ease
    4 KB (538 words) - 10:44, 22 May 2018
  • ...Poulsbo|l=chipset}} chipset which features the [[memory controller]], an [[integrated graphics]], and the various [[I/O]] ports. ...on-die, including the [[memory controller]], [[display controller]], and [[integrated graphics]]. Lincroft, along with the {{intel|Moorestown|l=platform}}, model
    17 KB (2,292 words) - 09:32, 16 July 2019
  • | max memory = 8 GiB ...end mobile system on chips. This chip supports up to 8 GiB of memory and [[integrated graphics processor|integrates]] the {{intel|HD Graphics 405}} GPU.
    4 KB (462 words) - 16:15, 13 December 2017
  • | max memory = 8 GiB ...end mobile system on chips. This chip supports up to 8 GiB of memory and [[integrated graphics processor|integrates]] the {{intel|HD Graphics (Cherry Trail)}} GP
    4 KB (472 words) - 16:15, 13 December 2017
  • |max memory=8 GiB ...equency of 1.04 GHz with a burst up to 2.0 GHz and supports up to 8 GiB of memory. This chip incorporates the {{intel|HD Graphics (Braswell)}} GPU.
    4 KB (475 words) - 17:42, 27 March 2018
  • | max memory = 8 GiB | max memory addr =
    5 KB (573 words) - 16:15, 13 December 2017
  • | max memory = 8 GiB | max memory addr =
    5 KB (572 words) - 16:15, 13 December 2017
  • | max memory = 2 GiB | max memory addr =
    6 KB (744 words) - 18:35, 14 January 2019
  • |max memory=2 GiB ...equency of 1.44 GHz with a burst up to 1.92 GHz and supports up to 2 GB of memory. This chip incorporates the {{intel|HD Graphics (Cherry Trail)}} GPU.
    5 KB (736 words) - 03:44, 19 August 2023
  • | max memory = 2 GiB | max memory addr =
    5 KB (558 words) - 16:15, 13 December 2017
  • | max memory = 1024 MB {{integrated graphic
    4 KB (424 words) - 16:15, 13 December 2017
  • | max memory = 2 GiB {{integrated graphic
    4 KB (449 words) - 16:15, 13 December 2017
  • | max memory = 2 GiB {{integrated graphic
    4 KB (467 words) - 16:15, 13 December 2017
  • | max memory = 2 GiB {{integrated graphic
    4 KB (418 words) - 16:15, 13 December 2017
  • | max memory = 2 GiB {{integrated graphic
    4 KB (412 words) - 16:15, 13 December 2017
  • === Memory Hierarchy === ...cute simultaneously such as in the case of instructions that performance a memory access along an arithmetic operation. In those instances Bonnell will issue
    38 KB (5,468 words) - 20:29, 23 May 2019
  • While the previous {{intel|Atom}} architecture did away with the memory controller by integrating and other support chips on-die, it still used a Front Side B === Memory Hierarchy ===
    9 KB (1,160 words) - 09:35, 25 September 2019
  • |max memory=8 GiB == Memory controller ==
    4 KB (529 words) - 17:41, 27 March 2018
  • |max memory=8 GiB == Memory controller ==
    5 KB (701 words) - 17:40, 27 March 2018
  • |max memory=8 GiB == Memory controller ==
    4 KB (540 words) - 17:40, 27 March 2018
  • |max memory=8 GiB == Memory controller ==
    4 KB (544 words) - 17:43, 27 March 2018
  • |max memory=8 GiB == Memory controller ==
    4 KB (580 words) - 09:40, 8 July 2022
  • |max memory=16 GiB == Memory controller ==
    5 KB (724 words) - 06:10, 2 December 2018
  • |max memory=8 GiB == Memory controller ==
    4 KB (539 words) - 17:39, 27 March 2018
  • |max memory=8 GiB == Memory controller ==
    4 KB (535 words) - 17:39, 27 March 2018
  • |max memory=8 GiB == Memory controller ==
    5 KB (722 words) - 01:50, 24 November 2018
  • |max memory=8 GiB == Memory controller ==
    4 KB (533 words) - 17:41, 27 March 2018
  • |max memory=8 GiB == Memory controller ==
    4 KB (539 words) - 17:39, 27 March 2018
  • |max memory=128 GiB ...f 2.6 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
    4 KB (593 words) - 02:17, 1 April 2019
  • |max memory=128 GiB ...f 2.6 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
    4 KB (593 words) - 02:18, 1 April 2019
  • |max memory=128 GiB ...Hz with a TDP of 35 W and supports up to 128 GiB of dual-channel DDR4-2133 memory.
    4 KB (582 words) - 02:21, 1 April 2019
  • |max memory=128 GiB ...f 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
    4 KB (596 words) - 02:18, 1 April 2019
  • |max memory=128 GiB ...f 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
    4 KB (595 words) - 02:16, 1 April 2019
  • |max memory=128 GiB ...f 2.5 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
    4 KB (595 words) - 02:16, 1 April 2019
  • |max memory=128 GiB ...f 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
    4 KB (593 words) - 02:17, 1 April 2019
  • |max memory=128 GiB ...f 2.3 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
    4 KB (595 words) - 02:16, 1 April 2019
  • |max memory=128 GiB ...f 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.
    4 KB (596 words) - 02:17, 1 April 2019
  • |max memory=128 GiB ...f 2.6 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.
    4 KB (595 words) - 09:36, 14 May 2021
  • |max memory=128 GiB ...f 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.
    4 KB (595 words) - 02:16, 1 April 2019
  • |max memory=128 GiB ...f 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
    4 KB (595 words) - 02:18, 1 April 2019
  • |max memory=128 GiB ...f 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.
    4 KB (595 words) - 02:16, 1 April 2019
  • |max memory=128 GiB ...f 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
    4 KB (595 words) - 02:17, 1 April 2019
  • * Platform Controller Hub (PCH) * Fully Integrated Voltage Regulator (FIVR)
    27 KB (3,750 words) - 06:57, 18 November 2023
  • | max memory = 8 GiB ...he chip is manufactured in [[45 nm process]]. The i7-920XM supports 8GB of memory and has a thermal design power of 55 W.
    4 KB (522 words) - 20:46, 4 October 2018
  • | max memory = 8 GiB ...he chip is manufactured in [[45 nm process]]. The i7-940XM supports 8GB of memory and has a thermal design power of 55 W.
    4 KB (537 words) - 15:01, 13 December 2019
  • ** Memory Subsystem * Integrated Graphics
    84 KB (13,075 words) - 00:54, 29 December 2020
  • ** CSI-2 for the integrated IPU (mobile SKUs) ** Memory Subsystem
    79 KB (11,922 words) - 06:46, 11 November 2022
  • * Memory ** Faster memory for mainstream desktops (i.e., {{intel|Kaby Lake S|l=core}}) DDR4-2400 (fro
    38 KB (5,431 words) - 10:41, 8 April 2024
  • * Memory *** 1.5x higher memory bandwidth (60 GB/s, up from 40 GB/s)
    23 KB (3,613 words) - 12:31, 20 June 2021
  • | max memory = 24 GiB ...ncy of up to 3.6 GHz for a single core. This chip supports up to 24 GiB of memory and has a thermal design power of 130 W.
    4 KB (415 words) - 16:24, 13 December 2017
  • | max memory = 24 GiB ...cy of up to 3.47 GHz for a single core. This chip supports up to 24 GiB of memory and has a thermal design power of 130 W.
    4 KB (415 words) - 16:24, 13 December 2017
  • | max memory = 24 GiB ...th a maximum turbo frequency of 3.6 GHz. This MPU supports up to 24 GiB of memory and has a thermal design power of 130 W.
    4 KB (419 words) - 16:24, 13 December 2017
  • | max memory = 24 GiB ...h a maximum turbo frequency of 3.73 GHz. This MPU supports up to 24 GiB of memory and has a thermal design power of 130 W.
    4 KB (414 words) - 16:24, 13 December 2017
  • | max memory = 64 GiB ...andy Bridge}} microarchitecture, this chip supports up to 64 GiB (DDR3) of memory and has a Thermal Design Power of 130 W.
    5 KB (517 words) - 23:32, 22 September 2019
  • | max memory = 64 GiB ...andy Bridge}} microarchitecture, this chip supports up to 64 GiB (DDR3) of memory and has a Thermal Design Power of 150 W.
    4 KB (456 words) - 16:24, 13 December 2017
  • |max memory=64 GiB ...h turbo frequency of 4 GHz for a single core, this chip supports 64 GiB of memory (DDR3) and has a TDP of 130 Watts.
    4 KB (492 words) - 23:23, 12 March 2019
  • | max memory = 64 GiB ...of up to 3.5 GHz for a single core. The i7-5960X supports up to 64 GiB of memory (DDR4). This processor was eventually replaced by {{\\|i7-6950X}}, a {{inte
    5 KB (524 words) - 16:24, 13 December 2017
  • |max memory=128 GiB This processor has no integrated graphics processing unit.
    4 KB (564 words) - 14:29, 24 March 2019
  • |max memory=32 GiB ...of 1.3 GHz. This processor supports up to 32 GiB of dual-channel DDR3-1600 memory.
    5 KB (710 words) - 16:24, 13 December 2017
  • |max memory=32 GiB ...of 1.3 GHz. This processor supports up to 32 GiB of dual-channel DDR3-1600 memory.
    5 KB (710 words) - 03:49, 26 June 2018
  • | max memory = 32 GiB ...ctured in [[22 nm process]] has a TDP of 55 W and supports up to 32 GiB of memory (DDR3).
    5 KB (573 words) - 16:24, 13 December 2017
  • |max memory=32 GiB ...ctured in [[22 nm process]] has a TDP of 55 W and supports up to 32 GiB of memory (DDR3).
    4 KB (558 words) - 23:13, 12 March 2019
  • | max memory = 32 GiB ...ctured in [[22 nm process]] has a TDP of 57 W and supports up to 32 GiB of memory (DDR3).
    5 KB (544 words) - 16:24, 13 December 2017

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