Page title matches

• dec/alpha (isa)
  #REDIRECT [[alpha]]
  19 bytes (2 words) - 18:29, 30 November 2017

Page text matches

• intel/microarchitectures/sandy bridge (client)
  |isa=x86-64 :<math>E_{n+1} = \alpha E_n + (1- \alpha) * (\text{TDP}_n - P_n) \Delta t_n</math>
  84 KB (13,075 words) - 23:54, 28 December 2020
• amd/microarchitectures/k7
  |isa=x86-32 ** K7 utilizes the [[Digital Alpha]] {{decc|EV6}} system bus interface
  6 KB (923 words) - 15:48, 3 March 2022
• mediatek/helio/mt6757
  |isa=ARMv8 |isa family=ARM
  4 KB (473 words) - 03:40, 23 June 2019
• mediatek/helio/mt6757cd
  |isa=ARMv8 |isa family=ARM
  4 KB (564 words) - 05:22, 30 March 2021
• dec/microarchitectures/strongarm
  |isa=ARMv4 ...two major microarchitectures developed by DEC around the same time ({{decc|Alpha 21264|l=arch}} being the second one). The primary design goal was to develo
  5 KB (738 words) - 12:49, 15 July 2018
• dec/microarchitectures/alpha 21264
  {{dec title|Alpha 21264|arch}} |name=Alpha 21264
  2 KB (244 words) - 05:59, 13 June 2017
• compaq/microarchitectures/alpha 21364
  {{compaq title|Alpha 21364|arch}} |name=Alpha 21364
  2 KB (258 words) - 19:41, 14 June 2017
• compaq/microarchitectures/alpha 21464
  {{compaq title|Alpha 21464|arch}} |name=Alpha 21464
  2 KB (228 words) - 12:20, 31 March 2019
• dec/microarchitectures/alpha 21164
  {{dec title|Alpha 21164|arch}} |name=Alpha 21164
  2 KB (206 words) - 10:52, 27 November 2020
• dec/microarchitectures/alpha 21064
  {{dec title|Alpha 21064|arch}} |name=Alpha 21064
  4 KB (527 words) - 01:09, 4 August 2017
• dec/alpha
  {{dec title|Alpha}} | title = Alpha
  3 KB (388 words) - 05:17, 18 June 2017
• alpha
  {{title|Alpha}} '''Alpha AXP''' or simply '''Alpha''' is a {{arch|64}} [[RISC]] [[instruction set architecture]] designed by [
  755 bytes (105 words) - 12:51, 15 July 2018
• vti/vl86cx/vl86c020
  |isa=ARMv2a |isa family=ARM
  2 KB (327 words) - 00:21, 7 November 2021
• qualcomm/snapdragon 800/855 plus
  |isa=ARMv8 |isa family=ARM
  6 KB (835 words) - 11:00, 17 July 2022
• alchemy/au1200-333mgc
  |isa=MIPS32 ...cessor with an {{alchemy|Au1|l=arch}} CPU core implementing the [[MIPS32]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semicon
  6 KB (862 words) - 00:16, 19 March 2022
• alchemy/au1200-333mgd
  |isa=MIPS32 ...cessor with an {{alchemy|Au1|l=arch}} CPU core implementing the [[MIPS32]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semicon
  6 KB (865 words) - 00:18, 19 March 2022
• alchemy/au1200-333mgf
  |isa=MIPS32 ...cessor with an {{alchemy|Au1|l=arch}} CPU core implementing the [[MIPS32]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semicon
  6 KB (872 words) - 00:19, 19 March 2022
• alchemy/au1200-333mgi
  |isa=MIPS32 ...cessor with an {{alchemy|Au1|l=arch}} CPU core implementing the [[MIPS32]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semicon
  6 KB (873 words) - 00:23, 19 March 2022
• alchemy/au1200-400mgc
  |isa=MIPS32 ...cessor with an {{alchemy|Au1|l=arch}} CPU core implementing the [[MIPS32]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semicon
  6 KB (859 words) - 00:24, 19 March 2022
• alchemy/au1200-400mgd
  |isa=MIPS32 ...cessor with an {{alchemy|Au1|l=arch}} CPU core implementing the [[MIPS32]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semicon
  6 KB (858 words) - 00:26, 19 March 2022

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