...core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room Initial Cannon Lake models were introduced in May 2018 with additional models planned throughout the year.

...ake U|l=core}} || ICL-U || Ultra-low Power || || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room ** New Gaussian Neural Accelerator 1.0 (Added in {{\\|Cannon Lake}} but unclear to what extent)

* TCP accelerator * QoS accelerator

...uding {{intel|Core i3|i3}}, {{intel|Core i5|i5}}, and {{intel|Core i7|i7}} models. ...ne 6: [[IBM]] announces a breakthrough in the mass manufacturing of [[gate-all-around|GAA FET]]-based [[5 nm process]]

...te [[machine learning]] algorithms, typically by operating on [[predictive models]] such as [[artificial neural network]]s (ANNs) or [[random forest]]s (RFs) ...tiated on a single chip, or they may be part of a dedicated neural-network accelerator.

...the {{movidius|SABRE}} test chip they've developed the prior year. All the models have the same basic features: Models: (most of the differences are in the video capabilities of the chip)

|atype=Accelerator ...reaming Hybrid Architecture Vector Engine v2.0''' ('''SHAVE v2.0''') is an accelerator microarchitecture designed by [[Movidius]] for their vision processors. SHA

{{intel title|Configurable Spatial Accelerator (CSA)}} '''Configurable Spatial Accelerator''' ('''CSA''') is an [[explicit data graph execution]] architecture designe

* [[Accelerator]] architecture (From self-hosted) ...r and workstation market. This is done through the use of [[PCIe]]-based [[accelerator cards]].

...package and come in two form factors: [[PCIe Gen 3]] and an [[OCP OAM]] [[accelerator card]]. {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Spring Crest]]

|feature=Hardware compression accelerator |feature 2=Hardware cryptography accelerator

...ice) in a power envelope of 10-50 W in order to main a light PCIe-driven [[accelerator card]] form factor such as [[M.2]]. The form factor and power envelope is s ...g independent inference workloads or they may be combined to handle larger models faster. Attached to each pair of ICEs and the {{intel|Sunny Cove|SNC|l=arch

...gine''' ('''VE''') is a family of [[vector processors]] designed as PCIe [[accelerator cards]] designed by [[NEC]]. ...r and nodes. With the introduction of the Vector Engine, NEC moved to an [[accelerator card]] architecture whereby a Vector Engine (VE) [[PCIe card]] are installe

...1210 and Au1250 with full production in Q2, and in January 2009 the Au13xx models integrating a graphics processor. In October 2009 RMI merged with [[NetLogi All processors of the Alchemy family use the {{alchemy|Au1|l=arch}} CPU core de