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From WikiChip
Isaiah - Microarchitectures - VIA Technologies
Edit Values | |
Isaiah µarch | |
General Info | |
Arch Type | CPU |
Designer | VIA Technologies |
Manufacturer | Fujitsu, TSMC |
Process | 65 nm, 40 nm |
Core Configs | 2, 4 |
Instructions | |
ISA | x86-64 |
Succession | |
Isaiah is the successor to Esther, an x86 microarchitecture designed by VIA Technologies for low power devices.
Brands
Family | |
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QuadCore |
Process Technology
Isaiah was originally fabricated on Fujitsu's 65 nm process and later undergone a process shrink to TSMC's 40 nm process.
Architecture
Key changes from Esther
- 65 nm (from 90 nm)
This list is incomplete; you can help by expanding it.
Retrieved from "https://en.wikichip.org/w/index.php?title=via_technologies/microarchitectures/isaiah&oldid=72579"
Facts about "Isaiah - Microarchitectures - VIA Technologies"
codename | Isaiah + |
core count | 2 + and 4 + |
designer | VIA Technologies + |
full page name | via technologies/microarchitectures/isaiah + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Fujitsu + and TSMC + |
microarchitecture type | CPU + |
name | Isaiah + |
process | 65 nm (0.065 μm, 6.5e-5 mm) + and 40 nm (0.04 μm, 4.0e-5 mm) + |