Edit Values
PEZY-SC4
General Info
Designer	PEZY
Manufacturer	TSMC
Model Number	PEZY-SC4
Market	Supercomputer
Introduction	2016 (announced) 2020 (launched)
General Specs
Family	PEZY-SCx
Frequency	1,600 MHz
Microarchitecture
Process	5 nm
Technology	CMOS
Die	740 mm²
Cores	16,384
Threads	131,072
Electrical
Power dissipation	640 W
Vcore	0.55 V

PEZY-SC4 (PEZY Super Computer 4) is a fifth generation many-core microprocessor developed by PEZY set to be introduced in the early-2020s. This chip, which is planned to operate at 1.6 GHz, will incorporate 16,384 cores and dissipate 640 W. The PEZY-SC4 will power the ZettaScaler-4.x series of supercomputers.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Overview

The SC4 will be introduced by PEZY along with their fourth-generation ZettaScaler-4.0 supercomputer series. The SC4 is set to incorporate 16,384 cores along with 8-way SMT support for a total of 131,072 threads, twice as many cores as its predecessor.

Operating at 1.6 GHz, the PEZY-SC4 will have a peak performance of 105 TFLOPS (single-precision) and 52.5 TFLOPS (double-precision) while consuming around 640 Watts. The PEZY-SC4 is expected to be manufactured on TSMC's 5 nm process.

Cache

This section is empty; you can help add the missing info by editing this page.

Memory controller

For main memory, the PEZY-SC4 supports 4 channels of 64-bit DDR5-4000 memory with ECC support for a total aggregated bandwidth of 107.3 GiB/s

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR5-4000 Supports ECC Yes Controllers 4 Channels 4 Width 64 bit Max Bandwidth 119.2 GiB/s 122,060.8 MiB/s 127.99 GB/s 127,990.025 MB/s 0.116 TiB/s 0.128 TB/s Bandwidth Single 29.8 GiB/s Double 59.6 GiB/s Quad 119.2 GiB/s

In addition to main memory bandwidth, the PEZY-SC4 supports Wide-IO with a width of 4,096 bit, twice of the SC3. As with the SC3, the SC4 will use ThruChip Interface (TCI) interfaces in order to communicate with the TCI-DRAM chips. This chip incorporates 8 interfaces, operating at 3 GHz for a bandwidth of 2.8 TiB/s per interface for a total aggregated bandwidth of 22.35 TB/s - twice the bandwidth of its predecessor.

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Memory Wide I/O Rate 3,000 MHz Width 4,096 bit Channels 8 Max Bandwidth 22.35 TiB/s 22,886.4 GiB/s 23,435,673.6 MiB/s 24,574.085 GB/s 24,574,084.881 MB/s 24.574 TB/s

Expansions

With the SC4, PEZY plans to expand on the custom optics interface that was designed for the PEZY-SC3 for up to 512 lanes.