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Xeon D-1612 - Intel
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Xeon D-1612
hewitt lake (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberD-1612
Part NumberGG8068204236701
S-SpecSRG06
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
ShopAmazon
General Specs
FamilyXeon D
SeriesD-1600
LockedYes
Frequency1,500 MHz
Turbo Frequency2,500 MHz (1 core)
Bus typeDMI 2.0
Clock multiplier15
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureBroadwell
PlatformGrangeville
Core NameHewitt Lake
Core Family6
Core Model6
Core SteppingA1
Process14 nm
Transistors3,200,000,000
TechnologyCMOS
Die246.24 mm²
Word Size64 bit
Cores4
Threads8
Max Memory128 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP22 W
Tjunction – 105 °C
Tcase – 92 °C
Packaging
PackageFCBGA-1667 (FCBGA)
Dimension37.5 mm × 37.5 mm × 3.557 mm
Pitch0.7 mm
Contacts1667
broadwell de (back).png

Xeon D-1612 is a 64-bit quad-core x86 microserver SoC introduced by Intel in early 2019. The D-1612 is based on the Broadwell microarchitecture and is fabricated on their 14 nm process. It operates at 1.5 GHz with a TDP of 22 W and a turbo frequency of 2.5 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.


Cache

Main article: Broadwell § Cache

[Edit/Modify Cache Info]

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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back

L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB8-way set associativewrite-back

L3$6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
  4x1.5 MiB16-way set associativewrite-back

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

[Edit/Modify Memory Info]

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Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Max Mem128 GiB
Controllers1
Channels2
Max Bandwidth31.78 GiB/s
32,542.72 MiB/s
34.124 GB/s
34,123.515 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.78 GiB/s

Expansions

[Edit/Modify Expansions Info]

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Expansion Options
PCIeRevision: 3.0
Max Lanes: 24
Configuration: x16, x8, x4
PCIeRevision: 2.0
Max Lanes: 8
Configuration: x8, x4
USBRevision: 3.0
Max Ports: 4
USBRevision: 2.0
Max Ports: 4
SATARevision: 3
Max Ports: 6


Networking

[Edit/Modify Network Info]

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Networking
Ethernet
10GbEYes (Ports: 4)

Features

[Edit/Modify Supported Features]

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Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
TXTTrusted Execution Technology (SMX)
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Facts about "Xeon D-1612 - Intel"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon D-1612 - Intel#pcie +
back imageFile:broadwell de (back).png +
base frequency1,500 MHz (1.5 GHz, 1,500,000 kHz) +
bus typeDMI 2.0 +
clock multiplier15 +
core count4 +
core family6 +
core model6 +
core nameHewitt Lake +
core steppingA1 +
designerIntel +
die area246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) +
familyXeon D +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon d/d-1612 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Secure Key Technology + and OS Guard +
has intel enhanced speedstep technologytrue +
has intel secure key technologytrue +
has intel supervisor mode execution protectiontrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description16-way set associative +
l3$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
ldateApril 2, 2019 +
main imageFile:hewitt lake (front).png +
manufacturerIntel +
market segmentServer +
max case temperature365.15 K (92 °C, 197.6 °F, 657.27 °R) +
max cpu count1 +
max junction temperature378.15 K (105 °C, 221 °F, 680.67 °R) +
max memory131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) +
max memory bandwidth31.78 GiB/s (32,542.72 MiB/s, 34.124 GB/s, 34,123.515 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max sata ports6 +
max usb ports4 +
microarchitectureBroadwell +
model numberD-1612 +
nameXeon D-1612 +
packageFCBGA-1667 +
part numberGG8068204236701 +
platformGrangeville +
process14 nm (0.014 μm, 1.4e-5 mm) +
s-specSRG06 +
seriesD-1600 +
smp max ways1 +
supported memory typeDDR4-2133 +
tdp22 W (22,000 mW, 0.0295 hp, 0.022 kW) +
technologyCMOS +
thread count8 +
transistor count3,200,000,000 +
turbo frequency (1 core)2,500 MHz (2.5 GHz, 2,500,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +