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Xeon D-1612
General Info
Designer	Intel
Manufacturer	Intel
Model Number	D-1612
Part Number	GG8068204236701
S-Spec	SRG06
Market	Server
Introduction	April 2, 2019 (announced) April 2, 2019 (launched)
Shop	Amazon
General Specs
Family	Xeon D
Series	D-1600
Locked	Yes
Frequency	1,500 MHz
Turbo Frequency	2,500 MHz (1 core)
Bus type	DMI 2.0
Clock multiplier	15
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Broadwell
Platform	Grangeville
Core Name	Hewitt Lake
Core Family	6
Core Model	6
Core Stepping	A1
Process	14 nm
Transistors	3,200,000,000
Technology	CMOS
Die	246.24 mm²
Word Size	64 bit
Cores	4
Threads	8
Max Memory	128 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	22 W
Tjunction	– 105 °C
Tcase	– 92 °C
Packaging
Package	FCBGA-1667 (FCBGA)
Dimension	37.5 mm × 37.5 mm × 3.557 mm
Pitch	0.7 mm
Contacts	1667

Xeon D-1612 is a 64-bit quad-core x86 microserver SoC introduced by Intel in early 2019. The D-1612 is based on the Broadwell microarchitecture and is fabricated on their 14 nm process. It operates at 1.5 GHz with a TDP of 22 W and a turbo frequency of 2.5 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.

Cache

Main article: Broadwell § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative write-back L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     4x256 KiB 8-way set associative write-back L3$ 6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB     4x1.5 MiB 16-way set associative write-back

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2133 Supports ECC Yes Max Mem 128 GiB Controllers 1 Channels 2 Max Bandwidth 31.78 GiB/s 32,542.72 MiB/s 34.124 GB/s 34,123.515 MB/s 0.031 TiB/s 0.0341 TB/s Bandwidth Single 15.89 GiB/s Double 31.78 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 24 Configuration: x16, x8, x4 PCIe Revision: 2.0 Max Lanes: 8 Configuration: x8, x4 USB Revision: 3.0 Max Ports: 4 USB Revision: 2.0 Max Ports: 4 SATA Revision: 3 Max Ports: 6

Networking

[Edit/Modify Network Info]

	Networking
	Ethernet 10GbE Yes (Ports: 4)

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology TXT Trusted Execution Technology (SMX) VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) TSX Transactional Synchronization Extensions Secure Key Secure Key Technology SMEP OS Guard Technology