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From WikiChip
Chivano - Microarchitectures - Intel
< intel | microarchitectures
| Edit Values | |
| Chivano µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Process | 90 nm |
| Instructions | |
| ISA | IA-64 |
| Succession | |
Chivano or Shavano was a planned Itanium microarchitecture set to be designed by Intel around the time Montecito was being developed. Chivano disappeared from Intel's roadmap and was ultimately cancelled or merged into another architecture due to unknown reasons.
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/chivano&oldid=68772"
Facts about "Chivano - Microarchitectures - Intel"
| codename | Chivano + |
| designer | Intel + |
| full page name | intel/microarchitectures/chivano + |
| instance of | microarchitecture + |
| instruction set architecture | IA-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Chivano + |
| process | 90 nm (0.09 μm, 9.0e-5 mm) + |