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Atom Z550 - Intel
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Atom Z550
silverthorne.png
Silverthorne chip
General Info
DesignerIntel
ManufacturerIntel
Model NumberZ550
Part NumberAC80566UE041DW
S-SpecSLGPT
QLNN (QS)
MarketMobile
IntroductionApril 8, 2009 (announced)
April 8, 2009 (launched)
ShopAmazon
General Specs
FamilyAtom
SeriesZ500
LockedYes
Frequency1999.99 MHz
Bus typeFSB
Bus speed133.33 MHz
Bus rate533.33 MT/s
Clock multiplier15
CPUID106C2
Microarchitecture
ISAx86-32 (x86)
MicroarchitectureBonnell
PlatformMenlow
ChipsetPoulsbo
Core NameSilverthorne
Core Family6
Core Model28
Core SteppingC0
Process45 nm
Transistors47,212,207
TechnologyCMOS
Die24.18 mm²
7.8 mm × 3.1 mm
Word Size32 bit
Cores1
Threads2
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation (average)220 mW
Power (idle)100 mW
Vcore0.75 V-1.1 V
TDP2.4 W
Tjunction0 °C – 90 °C
Tcase0 °C – 70 °C
Tstorage-40 °C – 85 °C
Packaging
PackageFCBGA-441 (FCBGA)
Dimension13 mm x 14 mm
Pin Count441
SocketBGA-441 (BGA)

Z550 is an ultra-low power 32-bit x86 microprocessor introduced by Intel in early 2009 specifically for Mobile Internet Devices (MID). The Z550, which is based on the Bonnell microarchitecture (Silverthorne core), is manufactured on a 45 nm process. This processor operates at 2 GHz with a TDP of just 2.4 W and an average power of 220 mW. The MPU features a legacy 533 MT/s front-side bus capable of communicating with the Poulsbo chipset in both low-power CMOS mode as well as normal GTL mode (which also works with other chipsets).

This processor has a TDP of 2.4 W when Hyper-Threading is disabled and 2.64 W when enabled.

Cache

Main article: Bonnell § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$56 KiB
57,344 B
0.0547 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$24 KiB
24,576 B
0.0234 MiB
1x24 KiB6-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB8-way set associative 

Memory controller

This processor has no integrated memory controller.

Graphics

This processor has no integrated graphics.

Features

Die Shot

See also: Bonnell § Silverthorne Die
  • 45 nm process
  • 9 metal layers
  • 47,212,207 transistors
  • 3.1 mm x 7.8 mm
  • 24.18 mm² die size

Silverthorne die shot.jpg


Silverthorne die shot (marked).png

Documents

Datasheet

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Facts about "Atom Z550 - Intel"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Atom Z550 - Intel#package +
base frequency1,999.99 MHz (2 GHz, 1,999,990 kHz) +
bus rate533.33 MT/s (0.533 GT/s, 533,330 kT/s) +
bus speed133.33 MHz (0.133 GHz, 133,330 kHz) +
bus typeFSB +
chipsetPoulsbo +
clock multiplier15 +
core count1 +
core family6 +
core model28 +
core nameSilverthorne +
core steppingC0 +
core voltage (max)1.1 V (11 dV, 110 cV, 1,100 mV) +
core voltage (min)0.75 V (7.5 dV, 75 cV, 750 mV) +
cpuid106C2 +
designerIntel +
die area24.18 mm² (0.0375 in², 0.242 cm², 24,180,000 µm²) +
die length7.8 mm (0.78 cm, 0.307 in, 7,800 µm) +
die width3.1 mm (0.31 cm, 0.122 in, 3,100 µm) +
familyAtom +
first announcedApril 8, 2009 +
first launchedApril 8, 2009 +
full page nameintel/atom/z550 +
has featureHyper-Threading Technology +, Enhanced SpeedStep Technology + and Intel VT-x +
has intel enhanced speedstep technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has simultaneous multithreadingtrue +
instance ofmicroprocessor +
isax86-32 +
isa familyx86 +
l1$ size56 KiB (57,344 B, 0.0547 MiB) +
l1d$ description6-way set associative +
l1d$ size24 KiB (24,576 B, 0.0234 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldateApril 8, 2009 +
main imageFile:silverthorne.png +
main image captionSilverthorne chip +
manufacturerIntel +
market segmentMobile +
max case temperature343.15 K (70 °C, 158 °F, 617.67 °R) +
max cpu count1 +
max junction temperature363.15 K (90 °C, 194 °F, 653.67 °R) +
max storage temperature358.15 K (85 °C, 185 °F, 644.67 °R) +
microarchitectureBonnell +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature233.15 K (-40 °C, -40 °F, 419.67 °R) +
model numberZ550 +
nameAtom Z550 +
packageFCBGA-441 +
part numberAC80566UE041DW +
platformMenlow +
power dissipation (average)0.22 W (220 mW, 2.9502e-4 hp, 2.2e-4 kW) +
power dissipation (idle)0.1 W (100 mW, 1.341e-4 hp, 1.0e-4 kW) +
process45 nm (0.045 μm, 4.5e-5 mm) +
s-specSLGPT +
s-spec (qs)QLNN +
seriesZ500 +
smp max ways1 +
socketBGA-441 +
tdp2.4 W (2,400 mW, 0.00322 hp, 0.0024 kW) +
technologyCMOS +
thread count2 +
transistor count47,212,207 +
word size32 bit (4 octets, 8 nibbles) +