From WikiChip
					
    Kunpeng 920-6426  - HiSilicon    
                	
														| Edit Values | |
| Kunpeng 920-6426 | |
| General Info | |
| Designer | HiSilicon | 
| Manufacturer | TSMC | 
| Model Number | 920-6426 | 
| Market | Server | 
| Introduction | September, 2018 (announced) January 7, 2019 (launched)  | 
| General Specs | |
| Family | Hi16xx | 
| Series | 920 | 
| Frequency | 2.6 GHz | 
| Microarchitecture | |
| ISA | ARMv8.2 (ARM) | 
| Microarchitecture | TaiShan v110 | 
| Core Name | TaiShan v110 | 
| Transistors | 20,000,000,000 | 
| Technology | CMOS | 
| MCP | Yes (3 dies) | 
| Word Size | 64 bit | 
| Cores | 64 | 
| Threads | 64 | 
| Max Memory | 2 TiB | 
| Multiprocessing | |
| Max SMP | 4-Way (Multiprocessor) | 
| Electrical | |
| TDP | 195 W | 
Kunpeng 920-6426 is a tetrahexaconta-core 64-bit ARM server microprocessor introduced by HiSilicon in early 2019. Fabricated by TSMC on a 7nm HPC process based on the TaiSHan v110 microarchitecture, this chip incorporates 64 cores operating at 2.6 GHz with a TDP of 180 W. This chip supports up to 2 TiB of octa-channel DDR4-2933 memory.
Expansions
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Features
[Edit/Modify Supported Features]
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 Supported ARM Extensions & Processor Features 
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Cache
- Main article: TaiShan v110 § Cache
 
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 Cache Organization  
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.  | 
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Memory controller
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 Integrated Memory Controller 
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Utilizing devices
- HiSilicon D06
 - TaiShan 2280
 - TaiShan 5280
 - TaiShan 5290
 - TaiShan X6000
 
This list is incomplete; you can help by expanding it.
Facts about "Kunpeng 920-6426  - HiSilicon"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.  | Kunpeng 920-6426 - HiSilicon#pcie + | 
| base frequency | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + | 
| core count | 64 + | 
| core name | TaiShan v110 + | 
| designer | HiSilicon + | 
| die count | 3 + | 
| family | Hi16xx + | 
| first announced | September 2018 + | 
| first launched | January 7, 2019 + | 
| full page name | hisilicon/kunpeng/920-6426 + | 
| has ecc memory support | true + | 
| instance of | microprocessor + | 
| is multi-chip package | true + | 
| isa | ARMv8.2 + | 
| isa family | ARM + | 
| l1$ size | 8,192 KiB (8,388,608 B, 8 MiB) + | 
| l1d$ size | 4,096 KiB (4,194,304 B, 4 MiB) + | 
| l1i$ size | 4,096 KiB (4,194,304 B, 4 MiB) + | 
| l2$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + | 
| l3$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + | 
| ldate | January 7, 2019 + | 
| main image | |
| manufacturer | TSMC + | 
| market segment | Server + | 
| max cpu count | 4 + | 
| max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + | 
| max memory bandwidth | 190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) + | 
| max memory channels | 8 + | 
| max sata ports | 2 + | 
| max usb ports | 4 + | 
| microarchitecture | TaiShan v110 + | 
| model number | 920-6426 + | 
| name | Kunpeng 920-6426 + | 
| series | 920 + | 
| smp max ways | 4 + | 
| supported memory type | DDR4-2933 + | 
| tdp | 195 W (195,000 mW, 0.261 hp, 0.195 kW) + | 
| technology | CMOS + | 
| thread count | 64 + | 
| transistor count | 20,000,000,000 + | 
| used by | HiSilicon D06 +, TaiShan 5280 +, TaiShan 5290 +, TaiShan X6000 + and TaiShan 2280 + | 
| word size | 64 bit (8 octets, 16 nibbles) + |