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ET-Minion - Microarchitectures - Esperanto
Edit Values | |
ET-Minion µarch | |
General Info | |
Arch Type | CPU |
Designer | Esperanto |
Manufacturer | TSMC |
Introduction | 2018 |
Process | 7 nm |
Pipeline | |
Type | Superscalar, Pipelined |
OoOE | No |
Speculative | Yes |
Reg Renaming | No |
Instructions | |
ISA | RV64 |
Extensions | I, M, A, F, D, C |
Contemporary | |
ET-Maxion |
ET-Minion is an energy-efficient RISC-V microarchitecture designed by Esperanto. ET-Minion is also sold as a licensable IP core.
Process Technology
ET-Minion is designed and optimized for TSMC's 7 nm process although it may be back-ported to older nodes in the future.
Architecture
ET-Minion is designed to deliver the best TeraFLOP per Watt efficiency. That is, this core was designed to achieve the highest floating point throughput with a high degree of energy efficiency.
- In-order pipeline
- Multi-thread
- Integrated vector floating point unit
- Extension for Tensor instructions
- Extension for graphics operations
- Support for hardware accelerators
Block Diagram
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy
This section is empty; you can help add the missing info by editing this page. |
Facts about "ET-Minion - Microarchitectures - Esperanto"
codename | ET-Minion + |
designer | Esperanto + |
first launched | 2018 + |
full page name | esperanto/microarchitectures/et-minion + |
instance of | microarchitecture + |
instruction set architecture | RV64 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | ET-Minion + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |