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Cavium CN5745-600 SSP
General Info
Designer	Cavium
Manufacturer	TSMC
Model Number	CN5745-600 SSP
Part Number	CN5745-600BG1217-SSP
Market	Storage
Introduction	Jun 26, 2007 (announced) August, 2007 (launched)
General Specs
Family	OCTEON Plus
Series	CN57xx
Frequency	600 MHz
Microarchitecture
ISA	MIPS64 (MIPS)
Microarchitecture	cnMIPS
Process	90 nm
Technology	CMOS
Word Size	64 bit
Cores	10
Threads	10
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Packaging
Package FCBGA-1217 (BGA) Dimension 40 mm x 40 mm Ball Count 1217 Interconnect BGA-1217

CN5745-600 SSP is a 64-bit deca-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates ten cnMIPS cores, operates at 600 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 480 KiB 491,520 B 0.469 MiB L1I$ 320 KiB 327,680 B 0.313 MiB 10x32 KiB     L1D$ 160 KiB 163,840 B 0.156 MiB 10x16 KiB     L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     1x2 MiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR2-800 Supports ECC Yes Controllers 1 Channels 2 Width 64 bit Max Bandwidth 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s Bandwidth Single 5.96 GiB/s Double 11.92 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
	PCIe Revision 1.0 Max Lanes 8 Configs x4, x8 UART GP I/O Yes

Networking

Interface options:

• 8-lanes PCIe + 8-lanes PCIe
• 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
• 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]

[Edit/Modify Network Info]

	Networking
	MII XAUI Yes (Ports: 1) SGMII Yes (Ports: 4)

Hardware Accelerators

[Edit/Modify Accelerators Info]

	Hardware Accelerators
	Encryption Hardware Implementation Yes Types 3DES, AES-GCM, AES up to 256-bit, SHA-1, SHA-2 up to SHA-512, RSA up to 8192, DH Networking TCP Yes QoS Yes Compression Compression Yes Decompression Yes RAID RAID 5 Yes RAID 6 Yes

Block diagram

Datasheet

• OCTEON CN57XX Processors Product Brief