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Alchemy Au1500-400MBC | |
General Info | |
Designer | Alchemy |
Manufacturer | TSMC |
Model Number | Au1500-400MBC |
Part Number | Au1500-400MBC |
Market | Embedded |
Introduction | June 11, 2001 (announced) December 2001 (launched) |
Release Price | $43 (tray) |
General Specs | |
Family | Alchemy |
Frequency | 400 MHz |
Microarchitecture | |
ISA | MIPS32 |
Microarchitecture | Au1 |
Core Stepping | AB, AC, AD |
Process | 180 nm |
Technology | CMOS |
Word Size | 32 bit |
Cores | 1 |
Max Memory | 192 MiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Vcore | 1.5 V ± 5% |
VI/O | 3.3 V |
TDP (Typical) | 700 mW |
Tcase | 0 °C – 70 °C |
Tstorage | -40 °C – 125 °C |
Au1500-400MBC was a 32-bit ultra low power embedded microprocessor with an Au1 CPU core implementing the MIPS32 ISA. Designed by Alchemy Semiconductor and fabricated on a TSMC 180 nm LV process, this SoC operates at a base frequency of up to 400 MHz with a typical TDP of 700 mW. It was also available as a Pb-free version Au1500-400MBD.
Cache
- Main article: Au1 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Au1500 processors integrate two independent memory controllers, a DRAM controller which supports SDRAM, SMROM, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, PCMCIA/CompactFlash devices, and I/O peripherals such as an external LCD controller. SDRAM runs at one half of the frequency of the internal 32-bit System Bus, which runs at up to one half of the CPU core frequency.
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Integrated Memory Controller
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Expansions
- PCI 2.2 controller, 32-bit bus, 33 or 66 MHz
- USB 1.1 (OHCI) host controller, USB 1.1 device controller
- Two USB host ports and one device port
- Two 10/100 Mbit/s Ethernet MAC controllers
- Low speed interfaces AC97, 2 × UART, and up to 39 GPIOs
Graphics
This processor has no integrated graphics processing unit.
Features
- 8-channel DMA engine
- RTC and TOY timer
- Two interrupt controllers
- Power management unit
- MIPS EJTAG interface
- Idle Mode, Sleep Mode
Package
- 424-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
- 23 × 23 grid, 0.8 mm pitch, solder ball ⌀ 0.4 mm, 63Sn/37Pb
- 19 mm × 19 mm × 1.45 mm
Bibliography
- "Product Brief: AMD Alchemy™ Solutions Au1500™ Processor Family Internet Edge Processor", AMD Publ. #26329, Rev. D, 2003
- "AMD Alchemy™ Au1500™ Processor Data Book", AMD Publ. #30361, Rev. D, March 2006
- "AMD Alchemy™ Au1500™ Processor Specification Update", AMD Publ. #27362, Rev. E, June 2005
- "Qualification of the AMD Alchemy™ Au1500™ Processor", AMD Publ. #27364, Rev. B, March 2003
- Bassett, Paul. "Alchemy Au1x00", Hot Chips 14, August 19, 2002
base frequency | 400 MHz (0.4 GHz, 400,000 kHz) + |
core count | 1 + |
core stepping | AB +, AC + and AD + |
core voltage | 1.5 V (15 dV, 150 cV, 1,500 mV) + |
core voltage tolerance | 5% + |
designer | Alchemy + |
family | Alchemy + |
first announced | June 11, 2001 + |
first launched | December 2001 + |
full page name | alchemy/au1500-400mbc + |
has ecc memory support | false + |
instance of | microprocessor + |
io voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
isa | MIPS32 + |
l1$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
ldate | December 2001 + |
manufacturer | TSMC + |
market segment | Embedded + |
max case temperature | 343.15 K (70 °C, 158 °F, 617.67 °R) + |
max cpu count | 1 + |
max memory | 192 MiB (196,608 KiB, 201,326,592 B, 0.188 GiB, 1.831055e-4 TiB) + |
max memory bandwidth | 0.373 GiB/s (381.47 MiB/s, 0.4 GB/s, 400 MB/s, 3.637979e-4 TiB/s, 4.0e-4 TB/s) + |
max memory channels | 1 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Au1 + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
model number | Au1500-400MBC + |
name | Alchemy Au1500-400MBC + |
part number | Au1500-400MBC + |
process | 180 nm (0.18 μm, 1.8e-4 mm) + |
release price | $ 43.00 (€ 38.70, £ 34.83, ¥ 4,443.19) + |
release price (tray) | $ 43.00 (€ 38.70, £ 34.83, ¥ 4,443.19) + |
smp max ways | 1 + |
supported memory type | SDR-133 + |
tdp (typical) | 0.7 W (700 mW, 9.387e-4 hp, 7.0e-4 kW) + |
technology | CMOS + |
word size | 32 bit (4 octets, 8 nibbles) + |