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Alchemy Au1100-500MBD
General Info
Designer	Alchemy
Manufacturer	TSMC
Model Number	Au1100-500MBD
Part Number	Au1100-500MBDBA, Au1100-500MBDBC, Au1100-500MBDBD, Au1100-500MBDBE, Au1100-500MBDBF
Market	Embedded
Introduction	April 8, 2002 (launched)
General Specs
Family	Alchemy
Frequency	500 MHz
Microarchitecture
ISA	MIPS32
Microarchitecture	Au1
Core Stepping	BA, BC, BD, BE, BF
Process	130 nm
Technology	CMOS
Word Size	32 bit
Cores	1
Max Memory	192 MiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	1.22 V
VI/O	3.3 V
TDP (Typical)	400 mW
Tcase	0 °C – 70 °C
Tstorage	-40 °C – 125 °C

Au1100-500MBD was a 32-bit ultra low power embedded microprocessor with an Au1 CPU core implementing the MIPS32 ISA. Designed by Alchemy Semiconductor and fabricated on a TSMC 130 nm process, this SoC operates at a base frequency of up to 500 MHz with a typical TDP of 400 mW. It is the Pb-free version of the Au1100-500MBC.

Cache

Main article: Au1 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 32 KiB 32,768 B 0.0313 MiB L1I$ 16 KiB 16,384 B 0.0156 MiB 1 × 16 KiB 4-way set associative   L1D$ 16 KiB 16,384 B 0.0156 MiB 1 × 16 KiB 4-way set associative write-back

Memory controller

Au1100 processors integrate two independent memory controllers, a DRAM controller which supports 2.5 V / 3.3 V SDRAM, SMROM, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, PCMCIA/CompactFlash devices, and I/O peripherals such as an external LCD controller. SDRAM runs at one half of the frequency of the internal 32-bit System Bus, which runs at up to one half of the CPU core frequency.

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type SDR-133 Supports ECC No Max Mem 192 MiB Controllers 1 Channels 1 Width 32 bit Max Bandwidth 0.500 GB/s 0.466 GiB/s 476.837 MiB/s 500 MB/s 4.547474e-4 TiB/s 5.0e-4 TB/s

Expansions

• USB 1.1 (OHCI) host controller, USB 1.1 device controller
  • Two USB host ports and one device port
• One 10/100 Mbit/s Ethernet MAC controller
• Two Secure Digital/SDIO 1.1 controllers
• Low speed interfaces AC97, I2S, Fast IrDA, 2 × SSI, 3 × UART, and up to 48 GPIOs

Graphics

Au1100 processors integrate an LCD controller which supports panels with a resolution up to 800 × 600 pixels.

• TFT: 1/2/4/8-bit mono, 12/16-bit color (4:4:4/5:6:5 RGB)
• STN: 4/8-bit mono single-scan, 8-bit color single-scan, 16-bit color dual-scan
• Frame buffer formats:
  • 1/2/4/8-bpp palettized
  • 16-bpp 6:5:5, 5:6:5, 5:5:6, 5:5:5:1 RGBI
• Double buffering
• Hardware swivel (90, 180, 270 degrees) for up to 320 × 240 pixel displays
• Two PWM clocks to control contrast and brightness voltages

Features

• 8-channel DMA engine
• RTC and TOY timer
• Two interrupt controllers
• Power management unit
• MIPS EJTAG interface
• Idle Mode, Sleep Mode

Package

• 399-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
• 20 × 20 grid, 0.8 mm pitch
• 17 mm × 17 mm × 1.7 mm

Bibliography

• "Product Brief: AMD Alchemy™ Solutions Au1100™ Processor Family Internet Edge Processor", AMD Publ. #26330, Rev. D, 2003
• "AMD Alchemy™ Au1100™ Processor Data Book", AMD Publ. #30362, Rev. D, April 2006
• "AMD Alchemy™ Au1100™ Processor Specification Update", AMD Publ. #27353, Rev. E, June 2005
• Bassett, Paul. "Alchemy Au1x00", Hot Chips 14, August 19, 2002