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From WikiChip
intel/microarchitectures/cascade lake
< intel | microarchitectures
Revision as of 19:46, 10 January 2020 by 108.49.66.128 (talk) (Replaced content with "DICK IS YuMMY")
DICK IS YuMMY
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/cascade_lake&oldid=95476"
Facts about "Cascade Lake - Microarchitectures - Intel"
| codename | Cascade Lake + |
| core count | 2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 +, 28 +, 32 +, 48 + and 56 + |
| designer | Intel + |
| first launched | 2019 + |
| full page name | intel/microarchitectures/cascade lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Cascade Lake + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |