Semiconductor & Computer Engineering
-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Mars II - Microarchitectures - Phytium
< phytium
| Edit Values | |
| Mars II µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Phytium |
| Manufacturer | TSMC |
| Introduction | 2019 |
| Process | 16 nm |
| Core Configs | 64 |
| Pipeline | |
| Type | Superscalar, Pipelined |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | ARMv8 |
| Succession | |
Mars II is the successor to Mars I, an ARM server SoC microarchitecture designed by Phytium Technology for the Chinese server market.
Process technology
 |
This section is empty; you can help add the missing info by editing this page. |
Architecture
| |
This section is empty; you can help add the missing info by editing this page. |
Overview
| |
This section is empty; you can help add the missing info by editing this page. |
Die
- 16 nm process (16FF+) GL
- 1 Poly, 11 Metal layers, RDL
- 6,000,000,000 transistors
- 370 mm² die size
.png)
Retrieved from "https://en.wikichip.org/w/index.php?title=phytium/microarchitectures/mars_ii&oldid=86633"
Hidden category:
Facts about "Mars II - Microarchitectures - Phytium"
| codename | Mars II + |
| core count | 64 + |
| designer | Phytium + |
| first launched | 2019 + |
| full page name | phytium/microarchitectures/mars ii + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Mars II + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) + |