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02CY771
General Info
Designer	IBM
Manufacturer	GlobalFoundries
Model Number	02CY771
Part Number	02CY771
Market	Server, Workstation
Introduction	November, 2017 (announced) November, 2017 (launched)
General Specs
Family	POWER
Series	POWER9
Frequency	2.20 GHz
Turbo Frequency	3.80 GHz
Microarchitecture
ISA	Power ISA v3.0B (Power ISA)
Microarchitecture	POWER9
Core Name	Sforza
Process	14 nm
Transistors	8,000,000,000
Technology	CMOS
Die	693.37 mm² 25.228 mm × 27.48416 mm
Word Size	64 bit
Cores	12
Threads	48
Max Memory	2 TiB
Multiprocessing
Max SMP	2-Way (Multiprocessor)
Electrical
TDP	105 W
Tjunction	0 °C – 85 °C
Packaging
Package	FCLGA-2601 (PLGA)
Dimension	50 mm × 50 mm
Pitch	1.016 mm
Contacts	2601

POWER9 02CY771 is a 12-core POWER server and workstation microprocessor designed by IBM and introduced in late 2017. This chip is based on the POWER9 microarchitecture and is fabricated on GlobalFoundries 14nm SOI Process. The 02CY771 has a base frequency of 2.2 GHz with a bost frequency of 3.80 GHz and a TDP of 105 W.

Cache

Main article: POWER9 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 768 KiB 786,432 B 0.75 MiB L1I$ 384 KiB 393,216 B 0.375 MiB 12x32 KiB 8-way set associative   L1D$ 384 KiB 393,216 B 0.375 MiB 12x32 KiB 8-way set associative   L2$ 3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB     6x512 KiB 8-way set associative   L3$ 60 MiB 61,440 KiB 62,914,560 B 0.0586 GiB     6x10 MiB 20-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC No Max Mem 2 TiB Controllers 2 Channels 8 Max Bandwidth 158.95 GiB/s 162,764.8 MiB/s 170.671 GB/s 170,671.263 MB/s 0.155 TiB/s 0.171 TB/s Bandwidth Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s Octa 158.95 GiB/s

[Edit] Memory Configurations
Configuration	Speed
One DIMM per channel	2666 MHz
Two DIMMs per channel	2400 MHz

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 4.0 Max Lanes: 48 Configuration: x16, x8, x4

Die

See also: POWER9 § Die

A die shot of IBM's 22-core server microprocessor used in this part: