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X-Gene 2 APM883832-X3 - AppliedMicro
Edit Values | |
APM883832-X3 | |
General Info | |
Designer | AppliedMicro |
Manufacturer | TSMC |
Model Number | APM883832-X3 |
Market | Server |
Introduction | March 08, 2017 (announced) |
General Specs | |
Turbo Frequency | 3,000 MHz |
Microarchitecture | |
ISA | ARMv8 (ARM) |
Microarchitecture | Skylark |
Process | 16 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 32 |
Threads | 32 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Vcore | 0.85 V |
VI/O | 1.8, 3.3 |
TDP | 125 W |
Tjunction | 0 °C – 90 °C |
APM883208-X2 is a 64-bit 32-core ARM server microprocessor designed by AppliedMicro and announced in 2016. Fabricated on TSMC's 16 nm process based on the Skylark microarchitecture, this processor features 32 custom ARMv8 cores operating at up to 3 GHz with a TDP of 125 W. This chip supports up to 1 TiB of octa-channel DDR4-2666 memory.
This processor was only sampled and never made it to general availability. Ths IP was eventually sold to Ampere Computing which re-introduced the chip under the eMAG 8180 name.
Contents
Cache
- Main article: Skylark § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options |
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Features
[Edit/Modify Supported Features]
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Supported ARM Extensions & Processor Features
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Facts about "X-Gene 3 APM883832-X3 - AppliedMicro"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | X-Gene 3 APM883832-X3 - AppliedMicro#pcie + |
core count | 32 + |
core voltage | 0.85 V (8.5 dV, 85 cV, 850 mV) + |
designer | AppliedMicro + |
first announced | March 8, 2017 + |
full page name | apm/x-gene/apm883832-x3 + |
has ecc memory support | true + |
instance of | microprocessor + |
io voltage | 1.8 V (18 dV, 180 cV, 1,800 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) + |
isa | ARMv8 + |
isa family | ARM + |
l1$ size | 2,048 KiB (2,097,152 B, 2 MiB) + |
l1d$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1i$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
l3$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |
ldate | March 8, 2017 + |
manufacturer | TSMC + |
market segment | Server + |
max cpu count | 1 + |
max junction temperature | 363.15 K (90 °C, 194 °F, 653.67 °R) + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) + |
max memory channels | 8 + |
max sata ports | 4 + |
max usb ports | 2 + |
microarchitecture | Skylark + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | APM883832-X3 + |
name | APM883832-X3 + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |
smp max ways | 1 + |
supported memory type | DDR4-2666 + and DDR4-2400 + |
tdp | 125 W (125,000 mW, 0.168 hp, 0.125 kW) + |
technology | CMOS + |
thread count | 32 + |
turbo frequency | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |