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APM883208-X2
General Info
Designer	AppliedMicro
Manufacturer	TSMC
Model Number	APM883208-X2
Market	Server
Introduction	September, 2014 (announced) March, 2015 (launched)
General Specs
Family	X-Gene
Series	X-Gene 2
Turbo Frequency	2,400 MHz
Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Shadowcat
Process	28 nm
Technology	CMOS
Word Size	64 bit
Cores	8
Threads	8
Max Memory	256 GiB
Electrical
Vcore	0.9 V
VI/O	1.8 V, 2.5 V, 3.3 V
TDP	35 W
Tjunction	0 °C – 90 °C

APM883208-X2 is a 64-bit octa-core ARM server microprocessor designed by AppliedMicro and introduced in 2014. Fabricated on TSMC 28 nm process based on the Shadowcat microarchitecture, this processor has eight custom ARMv8 cores operating at up to 2.4 GHz and supporting up to 256 GiB of dual-channel DDR3-1866 memory.

Cache

Main article: Shadowcat § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 512 KiB 524,288 B 0.5 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative   L1D$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative Write-through with write-combine L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     4x256 KiB     L3$ 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB     1x8 MiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1866 Supports ECC Yes Max Mem 256 GiB Controllers 1 Channels 2 Max Bandwidth 27.82 GiB/s 28,487.68 MiB/s 29.871 GB/s 29,871.498 MB/s 0.0272 TiB/s 0.0299 TB/s Bandwidth Single 13.91 GiB/s Double 27.82 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 17 Configuration: 1x16+x1, 2x8+x1 USB Revision: 2.0 Max Ports: 2 SATA Revision: 3.0 Max Ports: 6

• 2x I2C
• 4x UARTs
• GPIOs
• 2x SPI
• 2x SDIO 3.0
• JTAG / Trace

Network

[Edit/Modify Network Info]

	Networking
	MII RGMII Yes (Ports: 4) SGMII Yes (Ports: 1)

• Note: some ports are muxed

Block diagram