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Cortex-A76 (Ares) - Microarchitectures - ARM
Edit Values | |
Cortex-A76 µarch | |
General Info | |
Arch Type | CPU |
Designer | ARM Holdings |
Manufacturer | TSMC |
Introduction | May 31, 2018 |
Process | 10 nm, 7 nm |
Core Configs | 1, 2, 4 |
Pipeline | |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 11-13 |
Decode | 4-way |
Instructions | |
ISA | ARMv8.2 |
Extensions | FPU, NEON |
Cache | |
L1I Cache | 8-64 KiB/core 4-way set associative |
L1D Cache | 8-64 KiB/core 4-way set associative |
L2 Cache | 64-256-512 KiB/core |
L3 Cache | 0-4 MiB/Cluster |
Succession | |
Cortex-A76 (codename Ares) is the successor to the Cortex-A75, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A76, which implemented the ARMv8.2 ISA, is the a performant core which is often combined with a number of lower power cores (e.g. Cortex-A55) in a DynamIQ big.LITTLE configuration to achieve better energy/performance.
Facts about "Neoverse N1 - Microarchitectures - ARM"
codename | Cortex-A76 + |
core count | 1 +, 2 + and 4 + |
designer | ARM Holdings + |
first launched | May 31, 2018 + |
full page name | arm holdings/microarchitectures/neoverse n1 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-A76 + |
pipeline stages (max) | 13 + |
pipeline stages (min) | 11 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) + |