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Example Modules - Verilog
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Revision as of 13:16, 27 March 2018 by David (talk | contribs) (Created page with "{{verilog title|Example Modules}}{{verilog guide}} Below is a list of example {{\\|modules}}. == Examples == {| class="wikitable" |- ! Module !! Description |- | {{\|Adder}}...")
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Basics
Language
Gate Level Modeling
Behavioral Modeling
Testing
Modules
v · d · e

Below is a list of example modules.

Examples

Module Description
Adder
ALU
Counters
8-bit counter
LFSR counter
Memory
Single-port RAM
Dual-port RAM
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