Verilog

Basics

• Introduction
• History
• Syntax
• Number Representation

Language

• Keywords
• Identifiers
• Data types
• Compiler Directives
• System Tasks

Gate Level Modeling

• Primitives
• User Defined Primitives
• Operators

Behavioral Modeling

• Always Block
• Procedural Assignments
• Continuous Assignments
• Conditional Statement
• Case Statement
• Looping Statements
• Looping Statements

Testing

• Test Methodology
• Simulator
• Testbench

Modules

• Modules
• Example Modules