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Exynos 8 Octa
General Info
Designer	Samsung
Manufacturer	Samsung
Model Number	8890
Market	Mobile
Introduction	November 12, 2015 (announced) February 21, 2016 (launched)
General Specs
Family	Exynos
Series	8
Frequency	2,300 MHz
Turbo Frequency	2,600 MHz (1 core), 2,600 MHz (2 cores), 2,300 MHz (3 cores), 2,300 MHz (4 cores)
Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Mongoose 1, Cortex-A53
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	8
Threads	8
Max Memory	4 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)

Exynos 8 Octa (8890) is a 64-bit octa-core high-performance mobile SoC designed by Samsung and introduced in early 2016 for their consumer electronics. Manufactured on a 14 nm process, the 8890 features eight cores consisting of a big quad-core cluster operating at 2.3 GHz with a turbo of up to 2.6 GHz based on Samsung's custom Mongoose 1 microarchitecture and another little quad-core cluster operating at 1.6 GHz consisting of Cortex-A53 cores. This chip supports up to 4 GiB of dual-channel 32-bit LPDDR4-3600 memory and incorporates a Mali-T880 MP12 GPU operating at 650 MHz. The 8890 incorporates an LTE modem supporting cat 12 download and cat 13 upload.

Cache

Main articles: Mongoose 1 § Cache and Cortex-A53 § Cache

For the Mongoose 1 core cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 384 KiB 393,216 B 0.375 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 6x64 KiB 4-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative   L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     1x2 MiB 16-way set associative

For the Cortex-A53 cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 2-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 4-way set associative   L2$ 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB     1x256 KiB 16-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4-3600 Supports ECC No Max Mem 4 GiB Frequency 1800 MHz Controllers 2 Channels 2 Width 32 bit Bandwidth Single 13.41 GiB/s Double 26.82 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Mali-T880 Designer ARM Holdings Execution Units 12 Max Displays 2 Frequency 600 MHz 0.6 GHz 600,000 KHz Output DSI Standards DirectX 11.2 OpenCL 1.2 OpenGL ES 3.1