From WikiChip
Celeron J4005
Edit Values | |||||||
Celeron J4005 | |||||||
General Info | |||||||
Designer | Intel | ||||||
Manufacturer | Intel | ||||||
Model Number | J4005 | ||||||
Part Number | FH8068003067416 | ||||||
S-Spec | SR3S5 | ||||||
Market | Desktop | ||||||
Introduction | December 11, 2017 (announced) December 11, 2017 (launched) | ||||||
Release Price | $107.00 | ||||||
Shop | Amazon | ||||||
General Specs | |||||||
Family | Celeron | ||||||
Series | 4000 | ||||||
Locked | Yes | ||||||
Frequency | 2,000 MHz | ||||||
Turbo Frequency | 2,700 MHz (1 core) | ||||||
Clock multiplier | 20 | ||||||
Microarchitecture | |||||||
ISA | x86-64 (x86) | ||||||
Microarchitecture | Goldmont Plus | ||||||
Core Name | Gemini Lake | ||||||
Core Stepping | B0 | ||||||
Process | 14 nm | ||||||
Technology | CMOS | ||||||
Word Size | 64 bit | ||||||
Cores | 2 | ||||||
Threads | 2 | ||||||
Max Memory | 8 GiB | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Electrical | |||||||
TDP | 10 W | ||||||
Packaging | |||||||
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Celeron J4005 is a dual-core 64-bit x86 desktop microprocessor introduced by Intel in 2017. This processor is based on Goldmont Plus microarchitecture and is manufactured on a 14 nm process. The J4005 operates at 2 GHz with a burst frequency of 2.7 GHz and a TDP of 10 W. This MPU incorporates Intel's UHD Graphics 600 GPU operating at 250 MHz with a burst frequency of 750 MHz.
Cache
- Main article: Goldmont Plus § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Celeron J4005 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron J4005 - Intel#package + |
base frequency | 2,000 MHz (2 GHz, 2,000,000 kHz) + |
clock multiplier | 20 + |
core count | 2 + |
core name | Gemini Lake + |
core stepping | B0 + |
designer | Intel + |
family | Celeron + |
first announced | December 11, 2017 + |
first launched | December 11, 2017 + |
full page name | intel/celeron/j4005 + |
has locked clock multiplier | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 112 KiB (114,688 B, 0.109 MiB) + |
l1d$ description | 6-way set associative + |
l1d$ size | 48 KiB (49,152 B, 0.0469 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
ldate | December 11, 2017 + |
main image | + |
manufacturer | Intel + |
market segment | Desktop + |
max cpu count | 1 + |
max memory | 8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) + |
microarchitecture | Goldmont Plus + |
model number | J4005 + |
name | Celeron J4005 + |
package | FCBGA-1090 + |
part number | FH8068003067416 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 107.00 (€ 96.30, £ 86.67, ¥ 11,056.31) + |
s-spec | SR3S5 + |
series | 4000 + |
smp max ways | 1 + |
tdp | 10 W (10,000 mW, 0.0134 hp, 0.01 kW) + |
technology | CMOS + |
thread count | 2 + |
turbo frequency (1 core) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |