Template:mpu Core i3-9100 is a planned 64-bit mid-range performance x86 desktop processor by Intel set to be introduced in 2018. The i3-9100 is fabricated on Intel's 2nd generation 10nm+ process based on the Ice Lake microarchitecture.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

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Cache

Main article: Ice Lake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative write-back L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     4x256 KiB 4-way set associative write-back L3$ 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB     4x2 MiB 16-way set associative write-back