Template:mpu PEZY-SCnp (SC - Super Computer; np - New Package) is a revised version of the PEZY-SC model by PEZY introduced in may of 2016. The new chip, which made use of a slightly different package in order to address a number of signal-related issues (DRAM/PCIe signal failures). The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. Operating at 766 MHz, the processor has a peak performance of 3.14 TFLOPS (single-precision) and 157 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. As with the PEZY-SC, the SCnp is also manufactured on TSMC's 28HPC+.

Architecture

Further information: PEZY-SC § Architecture and PEZY-SCx § Architecture

The PEZY-SCnp's architecture is identical to the PEZY-SC.

Cache

PEZY-SC's cache is separate from the ARM926's cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared).

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 64 KiB 65,536 B 0.0625 MiB L1I$ 32 KiB 32,768 B 0.0313 MiB 2x16 KiB     L1D$ 32 KiB 32,768 B 0.0313 MiB 2x16 KiB     L2$ 64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB     1x64 KiB

The chip integrates a multi-level cache hierarchy:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 3 MiB 3,072 KiB 3,145,728 B L1I$ 2 MiB 2,048 KiB 2,097,152 B 1024x2 KiB per processor element   L1D$ 1 MiB 1,024 KiB 1,048,576 B 512x2 KiB per 2 processor elements   L2$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     4x2 MiB per city write-back L3$ 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB     4x2 MiB per prefecture

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2133 Supports ECC Yes Controllers 8 Channels 8 Width 64 bit Max Bandwidth 127.156 GiB/s 130,207.744 MiB/s 136.533 GB/s 136,532.715 MB/s 0.124 TiB/s 0.137 TB/s Bandwidth Single 15.89 GiB/s Double 31.79 GiB/s Quad 63.58 GiB/ Hexa 95.37 GiB/s Octa 127.156 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 32 Configuration: 4x8