Template:mpu PEZY-SC (PEZY Super Computer) is a second generation many-core microprocessor developed by PEZY and introduced in 2014. This chip, which operates at 733 MHz, incorporates 1,024 cores dissipating 100 W. The PEZY-SC powers the ZettaScaler-1.x series of supercomputers. The PEZY-SC is used in a number of TOP500 & Green500 supercomputers as the world's most efficient supercomputers.

Overview

See also: PEZY-1

The PEZY-SC (SC for "Super Computer") is PEZY's second generation microprocessors which builds upon the PEZY-1. The chip contains exactly twice as many cores and incorporates a large amount of cache including 8 MB of L3$. The chip contains 2 ARM926 cores (ARMv5TEJ) along with 1,024 simpler cores supporting 8-way SMT for a total of 8,192 threads. Operating at 733 MHz, the processor has a peak performance of 3.0 TFLOPS (single-precision) and 1.5 TFLOPS (double-precision). PEZY-SC was designed using 580 million gates and manufactured on TSMC's 28HPC+.

In June of 2015, PEZY-SC-based supercomputers took all top 3 spots on the Green500 listing as the 3 most efficient supercomputers. PEZY-SC powers Shoubu (1,181,952 cores, ? kW, 605.624 TFlop/s Linpack Rmax), and Suiren Blue (262,656 cores, 40.86 kW, 247.752 TFlop/s Linpack Rmax), and Suiren (328,480 cores, 48.90 kW, 271.782 TFlop/s Linpack Rmax) supercomputers (ranked 1, 2, and 3 respectively).

Architecture

Further information: PEZY-SCx § Architecture

The PEZY-SC microprocessors is made of 4 blocks called "Prefectures". The Prefecture contains 2 MiB of L3$ enclosed by 16 smaller blocks called "Cities". Each City is made of 64 KiB of L2$, a number of special function units, and 4 smaller blocks called "Villages". A village is a block of 4 execution units. For every 2 execution units there is 2 KiB of L1D$.

Cache

PEZY-SC's cache is separate from the ARM926's cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared).

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 3 MiB 3,072 KiB 3,145,728 B L1I$ 2 MiB 2,048 KiB 2,097,152 B 1024x2 KiB per processor element   L1D$ 1 MiB 1,024 KiB 1,048,576 B 512x2 KiB per 2 processor elements   L2$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     4x2 MiB per city write-back L3$ 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB     4x2 MiB per prefecture

Additionally, there is another 16 MiB consisting of 16 KiB per PE of scratch pad memory.

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2133 Supports ECC Yes Controllers 8 Channels 8 Width 64 bit Max Bandwidth 127.156 GiB/s 130,207.744 MiB/s 136.533 GB/s 136,532.715 MB/s 0.124 TiB/s 0.137 TB/s Bandwidth Single 15.89 GiB/s Double 31.79 GiB/s Quad 63.58 GiB/ Hexa 95.37 GiB/s Octa 127.156 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 2.0 Max Lanes: 32 Configuration: 4x8

Die Shot

• 28 nm process
• 19.5 mm × 21.1 mm
• 411.6 mm² die size

Floorplan

External Links

• Suiren Supercomputer on TOP500
• Shoubu Supercomputer on TOP500
• Suiren Blue on TOP500