Template:mpu QorIQ P1010 is a 32-bit embedded POWER microprocessor introduced by Freescale in 2008. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 667 MHz and supports 32-bit DDR2/3 memory.

Cache

Main article: e500 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 64 KiB 65,536 B 0.0625 MiB L1I$ 32 KiB 32,768 B 0.0313 MiB 1x32 KiB 8-way set associative   L1D$ 32 KiB 32,768 B 0.0313 MiB 1x32 KiB 8-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-800 Supports ECC Yes Controllers 1 Channels 1 Width 32 bit Max Bandwidth 2.98 GiB/s 3,051.52 MiB/s 3.2 GB/s 3,199.751 MB/s 0.00291 TiB/s 0.0032 TB/s Bandwidth Single 2.98 GiB/s

Expansions

• 2x 10/100/1000 Eithernet with SGMII
• 2x PCIe 1.0a controllers with 2 SerDes
• 2x USB 2.0
• SD/MMC
• SPI
• 2x I2C
• UART
• SEC 3.1 Security Acceleration

Block Diagram

Documents

• QorIQ P1 Series Product Brief