Template:mpu W-2195 is a 64-bit 18-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017. This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture, operates at 2.3 GHz with a TDP of 140 W and a turbo boost frequency of up to 4.3 GHz. This chip supports up to 512 GiB of hexa-channel DDR4-2666 ECC memory.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.125 MiB 1,152 KiB 1,179,648 B L1I$ 576 KiB 589,824 B 0.563 MiB 18x32 KiB 8-way set associative   L1D$ 576 KiB 589,824 B 0.563 MiB 18x32 KiB 8-way set associative write-back L2$ 18 MiB 18,432 KiB 18,874,368 B 0.0176 GiB     18x1 MiB 16-way set associative write-back L3$ 24.75 MiB 25,344 KiB 25,952,256 B 0.0242 GiB     18x1.375 MiB 11-way set associative write-back