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From WikiChip
Tigerlake - Microarchitectures - Intel
< intel | microarchitectures
Revision as of 16:44, 14 July 2017 by 60.49.33.29 (talk) (https://www.fool.com/investing/2017/07/14/key-detail-of-intel-corporation-tiger-lake-process.aspx "Per a LinkedIn profile of a current Intel employee, the company's Tiger Lake family of processors will include the company's Gen. 12 graphics architecture.")
Edit Values | |
Tigerlake µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | 2019 |
Process | 10 nm |
Succession | |
Tigerlake (TGL) is a planned microarchitecture by Intel as a successor to Icelake. Tigerlake is expected to be fabricated using a 10 nm process. Tigerlake is the "Optimization" microarchitecture as part of Intel's PAO model.
Process Technology
- Main article: Cannonlake § Process Technology
Tigerlake is set to use the same 10 nm process that was designed for Cannonlake.
Architecture
Not much is known about Tigerlake's architecture.
Key changes from Icelake
See also
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/tiger_lake&oldid=54782"
Facts about "Tiger Lake - Microarchitectures - Intel"
codename | Tigerlake + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/tiger lake + |
instance of | microarchitecture + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Tigerlake + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |