Template:mpu Xeon Platinum 8176 is a 64-bit 28-core x86 multi-socket highest performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8176, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.1 GHz with a TDP of 165 W and a turbo boost frequency of up to 3.8 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.75 MiB 1,792 KiB 1,835,008 B L1I$ 896 KiB 917,504 B 0.875 MiB 28x32 KiB 8-way set associative   L1D$ 896 KiB 917,504 B 0.875 MiB 28x32 KiB 8-way set associative write-back L2$ 28 MiB 28,672 KiB 29,360,128 B 0.0273 GiB     28x1 MiB 16-way set associative write-back L3$ 38.5 MiB 39,424 KiB 40,370,176 B 0.0376 GiB     28x1.375 MiB 11-way set associative write-back