x86
Instruction Set Architecture

General

• History
• Families

Variants

• x86-16
• x86-32
• x86-64

Topics

• Instructions
• Addressing Modes
• Registers
• Model-Specific Register
• Assembly
• Interrupts
• Micro-Ops
• Timer
• Calling Convention
• Microarchitectures
• CPUID

CPUIDs

• AMD's CPUIDs
• Intel's CPUIDs

Modes

• Real
• Protected
• Long

Extensions(all)

• 3DNow!
• ABM
• ADX
• AES
• AMX
• AVX
• AVX2
• AVX-512
• BMI1
• BMI2
• CLMUL
• E3DNow!
• EMMX
• F16C
• FMA3
• FMA4
• FPU
• MKTME
• MMX
• MPX
• PMEM
• PREFETCH
• RdRAND
• SEV
• SGX
• SHA
• SME
• SMM
• SMX
• SSE
• SSE2
• SSE3
• SSE4.1
• SSE4.2
• SSE4a
• SSE5
• SSSE3
• TBM
• TME
• TSME
• TSX
• XOP

AVX-512 is collective name for a number of 512-bit SIMD x86 instruction set extensions. The extensions was formally introduced by Intel in July 2013 with first general-purpose microprocessors implementing the extension introduced in July 2017.

Overview

AVX-512 is a set of 512-bit SIMD extensions that allow programs to pack sixteen single-precision eight double-precision floating-point numbers, or eight 64-bit or sixteen 32-bit integers within 512-bit vectors. The extension provides double the computation capabilities of that of AVX/AV2.

• AVX512F - AVX-512 Foundation is base of the 512-bit SIMD instruction extensions which is a comprehensive list of features for most HPC and enterprise applications. AVX-512 Foundation is the natural extensions to AVX/AVX2 which is extended using the EVEX prefix which builds on the existing VEX prefix. Any processor that implements any portion of the AVX-512 extensions MUST implement AVX512F.

• AVX512CD - AVX-512 Conflict Detection Instructions offer additional vectorization of loops with possible address conflict.

• AVX512DQ - AVX-512 Doubleword and Quadword Instructions add new 32-bit and 64-bit AVX-512 instructions

• AVX512PF - AVX-512 Prefetch Instructions add new prefetch instructions for gather/scatter and PREFETCHWT1 .

• AVX512ER - AVX-512 Exponential and Reciprocal Instructions (ERI) offer 28-bit precision RCP, RSQRT and EXP transcendentals for various scientific applications.

• AVX512VL - AVX-512 Vector Length Instructions add vector length orthogonality, allowing most AVX-512 operations to also operate on XMM (128-bit SSE) registers and YMM (256-bit AVX) registers

• AVX512BW - AVX-512 Byte and Word Instructions add support for for 8-bit and 16-bit integer operations.

• AVX512IFMA - AVX-512 Integer Fused Multiply-Add Instructions add support for fused multiply add of integers using 52-bit precision.

• AVX512VBMI - AVX-512 Vector Bit Manipulation Instructions add additional vector byte permutation instructions.

• AVX5124FMAPS - AVX-512 Fused Multiply Accumulation Packed Single precision Instructions add vector instructions for deep learning on floating-point single precision

• AVX5124VNNIW - AVX-512 Vector Neural Network Instructions Word Variable Precision Instructions add vector instructions for deep learning on enhanced word variable precision

• AVX512VPOPCNTDQ - AVX-512 Vector Population Count Doubleword and Quadword Instructions add double and quad word population count instructions.

Detection

CPUID		Instruction Set
Input	Output
EAX=07H, ECX=0	EBX[bit 16]	AVX512F
	EBX[bit 17]	AVX512DQ
	EBX[bit 21]	AVX512IFMA
	EBX[bit 26]	AVX512PF
	EBX[bit 27]	AVX512ER
	EBX[bit 28]	AVX512CD
	EBX[bit 30]	AVX512BW
	EBX[bit 31]	AVX512VL
	ECX[bit 01]	AVX512VBMI
	ECX[bit 14]	AVX512VPOPCNTDQ
	EDX[bit 02]	AVX5124VNNIW
	EDX[bit 03]	AVX5124FMAPS

Implementation

Designer	Microarchitecture	Support Level
		F	CD	ER	PF	BW	DQ	VL	IFMA	VBMI	4FMAPS	4VNNIW	VPOPCNTDQ
Intel	Knights Landing	✔	✔	✔	✔	✘	✘	✘	✘	✘	✘	✘	✘
	Knights Milll	✔	✔	✔	✔	✘	✘	✘	✘	✘	✔	✔	✔
	Skylake	✔	✔	✘	✘	✔	✔	✔	✘	✘	✘	✘	✘
	Cannonlake	✔	✔	✘	✘	✔	✔	✔	✔	✔	✘	✘	✘
	Icelake	✔	✔	✘	✘	✔	✔	✔	✔	✔	✘	✘	✘