| Edit Values |
| Xiaomi µarch |
|
| Arch Type | CPU |
| Designer | Phytium |
| Manufacturer | TSMC |
| Introduction | 2017 |
| Process | 28 nm |
|
| Type | Superscalar |
| Speculative | Yes |
| Reg Renaming | Yes |
|
| ISA | ARMv8 |
|
| Core Names | FTC660,
FTC661 |
Xiaomi is an ARM microarchitecture designed in-house by Phytium for their consumer market and server-based microprocessors.
Brands
| Codename |
Brand |
Description
|
| Mars |
FT-2000 |
- High performance
- High bandwidth, Large memory
- High bandwidth I/O
- Large scale cache coherency
|
| Earth |
FT-1500A |
- Moderate performance
- High power efficiency
- High density computing
- Low cost
|
Architecture
Overview
- Fully ARMv8 compatible
- Support AArch32 and AArch64 modes
- EL0-EL3 supported
- ASIMD-128
- 28 nm process
- Scalable design
- Mesh topology network-on-chip
- Panel-based (grid) architecture
- Global cache coherency
- 2x DDR3-1600 channels per panel
- 2x 16-lane PCIe 3.0
Panel Architecture
Phytium organizes their processors using a grid-layout they call Panels they call Panel-based data affinity architecture. Each panel consists of 8 independent ARMv8-compatible cores. Phytium "Mars" processor consists of 8 such panels for a total of 64 cores. Panels are interconnected with a 2-dimensional mesh network-on-a-chip level 2 cache with 4 MiB per panel for a total of 32 MiB.
In addition to the main die, Mars uses an additional Cache & Memory chips (CMC) auxiliary chips. "Mars" uses 8 such chips connected to the main die providing 16 MiB of level 3 cache for a total of 128 MiB as well as 8 dual-channel DDR3-1600 memory controllers for a total maximum bandwidth of 204 GB/s. Mars also provides two 16-lane PCIe 3.0 interfaces. The chips incorporates ECC and parity protection on all caches, tags, and TLBs.
Block Diagram
Memory Hierarchy
Pipeline
References
- Zhang, C. (2015, August). Mars: A 64-core ARMv8 processor. In Hot Chips 27 Symposium (HCS), 2015 IEEE (pp. 1-23). IEEE.
