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Gen9 LP µarch
General Info
Arch Type	GPU
Designer	Intel
Manufacturer	Intel
Introduction	August 5, 2015
Process	14 nm
Succession
Gen8 LP Gen9.5 LP

Gen9 LP (Generation 9 Low Power) is the microarchitecture for Intel's graphics processing unit utilized by Skylake-based microprocessors. Gen9 LP is the successor to Gen8 LP used by Broadwell. The Gen9 microarchitecture is designed separately by Intel and then integrated onto the same Skylake SoC die.

Codenames

Various models support different Graphics Tiers (GT) which provides different levels of performance. Some models also support an additional eDRAM side cache.

Code Name	Description
GT1	Contains 1 slice with 12 execution units.
GT2	Contains 1 slice with 24 execution units.
GT3	Contains 2 slices with 48 execution units.
GT3e	Contains 2 slices with 48 execution units. Has an additional eDRAM side cache.
Halo (GT4)	Contains 3 slices with 72 execution units.
Halo+e (GT4e)	Contains 3 slices with 72 execution units. Has an additional eDRAM side cache.

Brands

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Process Technology

Main article: Broadwell § Process Technology

Gen9 LP are part of the Skylake SoC die which uses the same 14 nm process used for the Broadwell microarchitecture.

Architecture

Gen9 LP presents a large departure from the Gen8 LP and previous architectures.

Key changes from Gen8 LP

• Architecture is drastically different
  • Gen9 LP is composed of 3 truely independent major components: Display block, Unslice, and the Slice.
• Unslice
  • Now sits on its own power gating/clock domain
    • Capable of running at higher speeds if the situation allows (irrespective of slice clock)
    • Can allow for pure fixed media alone
  • Higher throughput
  • Tessellator AutoStrip
  • Fixed function video encoder in the Quick Sync engine
  • codec (decode&encode) support for HEVC, VP8, MJPEG
  • RAW imaging capabilities
• Slice
  • L3 Cache
    • Increased to 768 KiB/slice (up from 576 KiB/slice)
    • Request queue size was increased
• Subslice
  • Adaptive scalable texture compression (ASTC)
  • 16x multi-sample anti-aliasing (MSAA)
  • Post depth test coverage mask
  • Multi-plane overlays
  • Texture samplers now natively support an NV12 YUV
  • Preemption of execution is now supported at the thread level
  • Round robin scheduling of threads within an execution unit.
  • new native support for the 32-bit float atomics operations of min, max, and compare/exchange.
  • 16-bit floating point capability is improved with native support for denormals and gradual underflow
• L4$
  • The eDRAM is now a side cache instead of an L4$ like it was in Gen8 LP. (See Skylake §eDRAM architectural changes for the reason)
  • Side-cache eDRAM was moved into the system agent adjacent to the display controller

Block Diagram

Entire SoC Overview

Gen9 LP

This block is for the most common setup, which is GT2 with 24 execution units.

Individual Core

See Skylake#Individual_Core.

Display

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Unslice

The Unslice is one of Gen9's major components and is responsible for the fixed-function geometry capabilities, fixed-function media capabilities, and it provides the interface to the memory fabric. One of the big changes in Gen9 is that the Unslice now sits on its own power/clock domain. This change allows the Unslice to operate at its own speed provided higher on-demand performance when desired. This change has a number of other benefits such as being able to turn off the slices (one or more) when they're not used in cases where pure fixed-function media is used. Additionally, the Unslice is now capable of running at a higher clock while the slice can run at a slower clock when the scenario demands it (such as in cases where higher fixed-function geometry or memory demands occur).

Slice

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