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Helio X10 (MT6795) - MediaTek
Template:mpu Helio X10 (MT6795) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and introduced in early-2014. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 28 nm process, operates at up to 2 GHz and supports dual-channel LPDDR3-933. This chip incorporates the PowerVR G6200 IGP operating at 700 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 4.
This SoC is made of 2 clusters of 4-core each (Cortex-A53) linked together via a CCI-400, a NEON engine, and Cortex-R4 core for the second MCU subsystem.
Contents
Cache
- Main article: Cortex-A53 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Graphics
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Integrated Graphics Information
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Wireless
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| 2G |
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| 3G |
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| 4G |
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Facts about "Helio X10 (MT6795) - MediaTek"
| has 2g support | true + |
| has 3g support | true + |
| has 4g support | true + |
| has csd support | true + |
| has dc-hsdpa support | true + |
| has e-utran support | true + |
| has ecc memory support | false + |
| has gprs support | true + |
| has hsupa support | true + |
| has lte advanced support | true + |
| has td-scdma support | true + |
| has umts support | true + |
| integrated gpu | PowerVR G6200 + |
| integrated gpu base frequency | 700 MHz (0.7 GHz, 700,000 KHz) + |
| integrated gpu designer | Imagination Technologies + |
| l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| max memory bandwidth | 13.9 GiB/s (14,233.6 MiB/s, 14.925 GB/s, 14,925.011 MB/s, 0.0136 TiB/s, 0.0149 TB/s) + |
| max memory channels | 2 + |
| supported memory type | DDR3-933 + |
| user equipment category | 4 + |