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From WikiChip
Xeon E5 - Intel
< intel
Intel Xeon E5 | |
Developer | Intel |
Manufacturer | Intel |
Type | Microprocessors |
Introduction | April 5, 2011 (announced) April 5, 2011 (launch) |
Architecture | Multi-socket server microprocessors |
ISA | x86-64 |
µarch | Westmere, Ivy Bridge, Haswell, Broadwell |
Word size | 64 bit 8 octets
16 nibbles |
Process | 32 nm 0.032 μm , 22 nm3.2e-5 mm 0.022 μm , 14 nm2.2e-5 mm 0.014 μm
1.4e-5 mm |
Technology | CMOS |
Clock | 1700 MHz-3400 MHZ |
Package | FCLGA-2011-v3 |
Socket | LGA-2011-v3 |
Xeon E5 is a family of mid-range enterprise-level x86 microprocessors. These server processors offer the high performance, multi-socket configuration support, and an extensive set of features. Various models are also used as high-end workstation microprocessors.
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5&oldid=26339"
Facts about "Xeon E5 - Intel"
designer | Intel + |
first announced | April 5, 2011 + |
first launched | April 5, 2011 + |
full page name | intel/xeon e5 + |
instance of | microprocessor family + |
instruction set architecture | x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Westmere +, Ivy Bridge +, Haswell + and Broadwell + |
name | Intel Xeon E5 + |
package | FCLGA-2011-v3 + |
process | 32 nm (0.032 μm, 3.2e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | LGA-2011-v3 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |