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From WikiChip
FastMATH 3 GHz - Intrinsity
< intrinsity | fastmath
Revision as of 15:25, 3 July 2016 by At32Hz (talk | contribs) (Created page with "{{intrinsity title|FastMATH 3 GHz}} The '''FastMATH 3 GHz''' was a microprocessor developed by Intrinsity operating at 3 GHz. The processor incorporates a high-performance...")
The FastMATH 3 GHz was a microprocessor developed by Intrinsity operating at 3 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit.
Retrieved from "https://en.wikichip.org/w/index.php?title=intrinsity/fastmath/fastmath-3&oldid=22659"
Facts about "FastMATH 3 GHz - Intrinsity"
base frequency | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
bus rate | 4,000 MT/s (4 GT/s, 4,000,000 kT/s) + |
bus speed | 500 MHz (0.5 GHz, 500,000 kHz) + |
bus type | RapidIO + |
core count | 1 + |
core voltage | 1.25 V (12.5 dV, 125 cV, 1,250 mV) + |
designer | Intrinsity + |
family | FastMATH + |
first announced | 2003 + |
full page name | intrinsity/fastmath/fastmath-3 + |
has feature | JTAG + |
instance of | microprocessor + |
l1d$ description | 256 blocks × 16 words/block + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 256 blocks × 16 words/block + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
ldate | 2003 + |
manufacturer | TSMC + |
market segment | Embedded + |
max memory | 1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) + |
microarchitecture | FashMATH + |
model number | FastMATH-3 + |
name | FastMATH 3 GHz + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
technology | Dynamic CMOS + |
thread count | 1 + |
word size | 32 bit (4 octets, 8 nibbles) + |