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FastMATH - Intrinsity
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FastMATH
fastmath chip.jpg
FastMATH and FastMIPS chips
Developer Intrinsity
Manufacturer TSMC
Type Microprocessors
Introduction 2000 (announced)
2002 (launch)
Architecture 32-bit vector/matrix math processor + RISC cpu
Word size 32 bit
4 octets
8 nibbles
Process 130 nm
0.13 μm
1.3e-4 mm
Technology CMOS
Clock 1 GHz-3 GHz
Package CBGA-670

FastMATH was a family of matrix and vector math processors with an on-die RISC CPUs introduced by Intrinsity. The chips were developed using Intrinsity's own proprietary Fast14 technology.

Architecture

Main article: FastMATH Microarchitecture

FastMATH was a series of microprocessors developed by Intrinsity using Fast14 technology - i.e. processors designed using custom dynamic domino logic. These chips incorporate the FastMIPS core along with a custom high-performance matrix and vector math coprocessor.

Matrix and Vector Math Processing Unit

The unit is designed as a single-instruction, multiple-data (SIMD) architecture capable of oeprating on 4x4 arrays of 32-bit values. Operates support fixed-point matrix, vector, and scalar data types with dedicated local register file. Data arrays are directly fetched from L2 cache.

  • Zero-cycle latency, two-cycle throughput
  • 64 GOPS (peak) at 2 GHz
  • 551,000 radix-4 1024-point 16-bit FFTs/sec at 2 GHz
  • 32 GMACs/sec at 2 GHz
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Documents

Evaluation Board

Manuals

White Paper

Facts about "FastMATH - Intrinsity"
designerIntrinsity +
first announced2000 +
first launched2002 +
full page nameintrinsity/fastmath +
instance ofmicroprocessor family +
main designerIntrinsity +
manufacturerTSMC +
nameFastMATH +
packageCBGA-670 +
process130 nm (0.13 μm, 1.3e-4 mm) +
technologyCMOS +
word size32 bit (4 octets, 8 nibbles) +