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FastMATH - Intrinsity
FastMATH was a family of matrix and vector math processors with an on-die RISC CPUs introduced by Intrinsity. The chips were developed using Intrinsity's own proprietary Fast14 technology.
Contents
Architecture
- Main article: FastMATH Microarchitecture
FastMATH was a series of microprocessors developed by Intrinsity using Fast14 technology - i.e. processors designed using custom dynamic domino logic. These chips incorporate the FastMIPS core along with a custom high-performance matrix and vector math coprocessor.
Matrix and Vector Math Processing Unit
The unit is designed as a single-instruction, multiple-data (SIMD) architecture capable of oeprating on 4x4 arrays of 32-bit values. Operates support fixed-point matrix, vector, and scalar data types with dedicated local register file. Data arrays are directly fetched from L2 cache.
- Zero-cycle latency, two-cycle throughput
- 64 GOPS (peak) at 2 GHz
- 551,000 radix-4 1024-point 16-bit FFTs/sec at 2 GHz
- 32 GMACs/sec at 2 GHz
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Documents
Manuals
White Paper
Facts about "FastMATH - Intrinsity"
designer | Intrinsity + |
first announced | 2000 + |
first launched | 2002 + |
full page name | intrinsity/fastmath + |
instance of | microprocessor family + |
main designer | Intrinsity + |
manufacturer | TSMC + |
name | FastMATH + |
package | CBGA-670 + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
technology | CMOS + |
word size | 32 bit (4 octets, 8 nibbles) + |