From WikiChip
Core M 5Y10
Template:mpu The Core M 5Y10 is an ultra-low power dual-core 64-bit x86 microprocessor introduced by Intel in 2014. This MPU operates at 800 MHz with a max turbo frequency of 2 GHz. This chip, which is manufactured in 14 nm process based on the Broadwell microarchitecture and incorporates Intel's HD Graphics 5300 Gen8 GPU clocked at 100 MHz with turbo frequency of 800 MHz.
Facts about "Core M 5Y10"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core M 5Y10#io + |
base frequency | 800 MHz (0.8 GHz, 800,000 kHz) + |
bus type | DMI 2.0 + |
clock multiplier | 8 + |
core count | 2 + |
core family | 06 + |
core model | 3D + |
core name | Broadwell Y + |
core stepping | E0 + |
designer | Intel + |
device id | 0x161E + |
die area | 82 mm² (0.127 in², 0.82 cm², 82,000,000 µm²) + |
drivers url | https://downloadcenter.intel.com/product/94028 + |
family | Core M + |
first launched | September 2, 2014 + |
full page name | intel/core m/5y10 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has extended page tables support | true + |
has feature | integrated gpu +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology + and Extended Page Tables + |
has intel enhanced speedstep technology | true + |
has intel turbo boost technology 2 0 | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | Intel HD Graphics 5300 + |
integrated gpu base frequency | 100 MHz (0.1 GHz, 100,000 KHz) + |
integrated gpu max frequency | 800 MHz (0.8 GHz, 800,000 KHz) + |
integrated gpu max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB) + |
isa | x86-64 + |
isa family | x86 + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 512 MiB (524,288 KiB, 536,870,912 B, 0.5 GiB) + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
ldate | September 2, 2014 + |
manufacturer | Intel + |
market segment | Mobile + |
max cpu count | 1 + |
max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) + |
max operating temperature | 95 °C + |
max pcie lanes | 12 + |
microarchitecture | Broadwell + |
min operating temperature | 0 °C + |
model number | 5Y10 + |
name | Core M 5Y10 + |
part number | FH8065802062002 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
s-spec | SR23C + |
series | 5000 + |
smp max ways | 1 + |
tdp | 4.5 W (4,500 mW, 0.00603 hp, 0.0045 kW) + |
technology | CMOS + |
thread count | 4 + |
transistor count | 1,300,000,000 + |
turbo frequency (1 core) | 2,000 MHz (2 GHz, 2,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |